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[src/trunk]: src/sys/arch/cobalt Merge forward from matt-nb5-mips64.
details: https://anonhg.NetBSD.org/src/rev/0c09404e73b0
branches: trunk
changeset: 762368:0c09404e73b0
user: matt <matt%NetBSD.org@localhost>
date: Sun Feb 20 07:54:10 2011 +0000
description:
Merge forward from matt-nb5-mips64.
(XXX generic kernels on raq2 die after interrupts are enabled but gxemul
works fine).
diffstat:
sys/arch/cobalt/cobalt/bus.c | 27 +++--
sys/arch/cobalt/cobalt/cpu.c | 16 ++-
sys/arch/cobalt/cobalt/interrupt.c | 160 ++++++++++++++---------------------
sys/arch/cobalt/cobalt/machdep.c | 53 ++++------
sys/arch/cobalt/conf/GENERIC | 10 +-
sys/arch/cobalt/conf/files.cobalt | 4 +-
sys/arch/cobalt/conf/std.cobalt | 3 +-
sys/arch/cobalt/dev/gt.c | 6 +-
sys/arch/cobalt/include/bootinfo.h | 6 +-
sys/arch/cobalt/include/intr.h | 51 +-----------
sys/arch/cobalt/pci/pci_machdep.c | 6 +-
sys/arch/cobalt/stand/boot/Makefile | 12 ++-
12 files changed, 141 insertions(+), 213 deletions(-)
diffs (truncated from 710 to 300 lines):
diff -r 0a7faf4fc936 -r 0c09404e73b0 sys/arch/cobalt/cobalt/bus.c
--- a/sys/arch/cobalt/cobalt/bus.c Sun Feb 20 07:52:42 2011 +0000
+++ b/sys/arch/cobalt/cobalt/bus.c Sun Feb 20 07:54:10 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bus.c,v 1.38 2009/12/14 00:46:00 matt Exp $ */
+/* $NetBSD: bus.c,v 1.39 2011/02/20 07:54:10 matt Exp $ */
/*
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.38 2009/12/14 00:46:00 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.39 2011/02/20 07:54:10 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -568,22 +568,24 @@
mips_dcache_wbinv_range(start, minlen);
break;
- case BUS_DMASYNC_PREREAD:
+ case BUS_DMASYNC_PREREAD: {
+ struct mips_cache_info * const mci = &mips_cache_info;
end = start + minlen;
- preboundary = start & ~mips_dcache_align_mask;
- firstboundary = (start + mips_dcache_align_mask)
- & ~mips_dcache_align_mask;
- lastboundary = end & ~mips_dcache_align_mask;
+ preboundary = start & ~mci->mci_dcache_align_mask;
+ firstboundary = (start + mci->mci_dcache_align_mask)
+ & ~mci->mci_dcache_align_mask;
+ lastboundary = end & ~mci->mci_dcache_align_mask;
if (preboundary < start && preboundary < lastboundary)
mips_dcache_wbinv_range(preboundary,
- mips_dcache_align);
+ mci->mci_dcache_align);
if (firstboundary < lastboundary)
mips_dcache_inv_range(firstboundary,
lastboundary - firstboundary);
if (lastboundary < end)
mips_dcache_wbinv_range(lastboundary,
- mips_dcache_align);
+ mci->mci_dcache_align);
break;
+ }
case BUS_DMASYNC_PREWRITE:
mips_dcache_wb_range(start, minlen);
@@ -606,12 +608,11 @@
bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs,
int flags)
{
- extern paddr_t avail_start, avail_end;
+ extern paddr_t mips_avail_start, mips_avail_end;
return (_bus_dmamem_alloc_range_common(t, size, alignment, boundary,
- segs, nsegs, rsegs, flags,
- avail_start /*low*/,
- avail_end - PAGE_SIZE /*high*/));
+ segs, nsegs, rsegs, flags,
+ mips_avail_start /*low*/, mips_avail_end - PAGE_SIZE /*high*/));
}
/*
diff -r 0a7faf4fc936 -r 0c09404e73b0 sys/arch/cobalt/cobalt/cpu.c
--- a/sys/arch/cobalt/cobalt/cpu.c Sun Feb 20 07:52:42 2011 +0000
+++ b/sys/arch/cobalt/cobalt/cpu.c Sun Feb 20 07:54:10 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.10 2008/05/09 10:59:55 tsutsui Exp $ */
+/* $NetBSD: cpu.c,v 1.11 2011/02/20 07:54:10 matt Exp $ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
@@ -28,18 +28,19 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.10 2008/05/09 10:59:55 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.11 2011/02/20 07:54:10 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
#include <sys/systm.h>
+#include <sys/cpu.h>
#include <machine/autoconf.h>
#include "ioconf.h"
-int cpu_match(device_t, cfdata_t, void *);
-void cpu_attach(device_t, device_t, void *);
+static int cpu_match(device_t, cfdata_t, void *);
+static void cpu_attach(device_t, device_t, void *);
CFATTACH_DECL_NEW(cpu, 0,
cpu_match, cpu_attach, NULL, NULL);
@@ -55,6 +56,11 @@
cpu_attach(device_t parent, device_t self, void *aux)
{
+ struct cpu_info * const ci = curcpu();
+
+ ci->ci_dev = self;
+ self->dv_private = ci;
+
aprint_normal(": ");
- cpu_identify();
+ cpu_identify(self);
}
diff -r 0a7faf4fc936 -r 0c09404e73b0 sys/arch/cobalt/cobalt/interrupt.c
--- a/sys/arch/cobalt/cobalt/interrupt.c Sun Feb 20 07:52:42 2011 +0000
+++ b/sys/arch/cobalt/cobalt/interrupt.c Sun Feb 20 07:54:10 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.5 2010/12/20 00:25:31 matt Exp $ */
+/* $NetBSD: interrupt.c,v 1.6 2011/02/20 07:54:10 matt Exp $ */
/*-
* Copyright (c) 2006 Izumi Tsutsui. All rights reserved.
@@ -79,7 +79,9 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.5 2010/12/20 00:25:31 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.6 2011/02/20 07:54:10 matt Exp $");
+
+#define __INTR_PRIVATE
#include <sys/param.h>
#include <sys/malloc.h>
@@ -137,11 +139,26 @@
static int icu_intr(void *);
static void icu_set(void);
+static const struct ipl_sr_map cobalt_ipl_sr_map = {
+ .sr_bits = {
+ [IPL_NONE] = MIPS_INT_MASK_0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0 | MIPS_INT_MASK_0,
+ [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0 | MIPS_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0,
+ [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0,
+ [IPL_VM] = MIPS_INT_MASK ^ MIPS_INT_MASK_5,
+ [IPL_SCHED] = MIPS_INT_MASK,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
+};
+
void
intr_init(void)
{
int i;
+ ipl_sr_map = cobalt_ipl_sr_map;
/*
* Initialize CPU interrupts.
*/
@@ -386,110 +403,65 @@
}
}
-void
-cpu_intr(uint32_t status, uint32_t cause, vaddr_t pc, uint32_t ipending)
+static void inline
+intr_handle(struct cpu_intrhead *intr)
{
- struct clockframe cf;
- struct cobalt_intrhand *ih;
- struct cpu_info *ci;
- uint32_t handled;
-
- handled = 0;
- ci = curcpu();
- ci->ci_idepth++;
- ci->ci_data.cpu_nintr++;
-
- if (ipending & MIPS_INT_MASK_5) {
- /* call the common MIPS3 clock interrupt handler */
- cf.pc = pc;
- cf.sr = status;
- mips3_clockintr(&cf);
-
- handled |= MIPS_INT_MASK_5;
+ struct cobalt_intrhand * const ih = &intr->intr_ih;
+ if (__predict_true(ih->ih_func != NULL)
+ && __predict_true((*ih->ih_func)(ih->ih_arg))) {
+ intr->intr_evcnt.ev_count++;
}
- _splset((status & handled) | MIPS_SR_INT_IE);
+}
- if (__predict_false(ipending & MIPS_INT_MASK_0)) {
- /* GT64x11 timer0 */
- volatile uint32_t *irq_src =
- (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_INTR_CAUSE);
+void
+cpu_intr(int ppl, vaddr_t pc, uint32_t status)
+{
+ uint32_t pending;
+ int ipl;
+
+ curcpu()->ci_data.cpu_nintr++;
- if (__predict_true((*irq_src & T0EXP) != 0)) {
- /* GT64x11 timer is no longer used for hardclock(9) */
- *irq_src = 0;
+ while (ppl < (ipl = splintr(&pending))) {
+ splx(ipl);
+ if (pending & MIPS_INT_MASK_5) {
+ struct clockframe cf;
+ /* call the common MIPS3 clock interrupt handler */
+ cf.pc = pc;
+ cf.sr = status;
+ cf.intr = (curcpu()->ci_idepth > 1);
+ mips3_clockintr(&cf);
}
- handled |= MIPS_INT_MASK_0;
- }
- if (ipending & MIPS_INT_MASK_3) {
- /* 16650 serial */
- ih = &cpu_intrtab[3].intr_ih;
- if (__predict_true(ih->ih_func != NULL)) {
- if (__predict_true((*ih->ih_func)(ih->ih_arg))) {
- cpu_intrtab[3].intr_evcnt.ev_count++;
+ if (__predict_false(pending & MIPS_INT_MASK_0)) {
+ /* GT64x11 timer0 */
+ volatile uint32_t *irq_src =
+ (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_INTR_CAUSE);
+
+ if (__predict_true((*irq_src & T0EXP) != 0)) {
+ /* GT64x11 timer is no longer used for hardclock(9) */
+ *irq_src = 0;
}
}
- handled |= MIPS_INT_MASK_3;
- }
- _splset((status & handled) | MIPS_SR_INT_IE);
- if (ipending & MIPS_INT_MASK_1) {
- /* tulip primary */
- ih = &cpu_intrtab[1].intr_ih;
- if (__predict_true(ih->ih_func != NULL)) {
- if (__predict_true((*ih->ih_func)(ih->ih_arg))) {
- cpu_intrtab[1].intr_evcnt.ev_count++;
- }
+ if (pending & MIPS_INT_MASK_3) {
+ /* 16650 serial */
+ intr_handle(&cpu_intrtab[3]);
}
- handled |= MIPS_INT_MASK_1;
- }
- if (ipending & MIPS_INT_MASK_2) {
- /* tulip secondary */
- ih = &cpu_intrtab[2].intr_ih;
- if (__predict_true(ih->ih_func != NULL)) {
- if (__predict_true((*ih->ih_func)(ih->ih_arg))) {
- cpu_intrtab[2].intr_evcnt.ev_count++;
- }
+
+ if (pending & MIPS_INT_MASK_1) {
+ /* tulip primary */
+ intr_handle(&cpu_intrtab[1]);
}
- handled |= MIPS_INT_MASK_2;
- }
- if (ipending & MIPS_INT_MASK_4) {
- /* ICU interrupts */
- ih = &cpu_intrtab[4].intr_ih;
- if (__predict_true(ih->ih_func != NULL)) {
- if (__predict_true((*ih->ih_func)(ih->ih_arg))) {
- cpu_intrtab[4].intr_evcnt.ev_count++;
- }
+ if (pending & MIPS_INT_MASK_2) {
+ /* tulip secondary */
+ intr_handle(&cpu_intrtab[2]);
}
- handled |= MIPS_INT_MASK_4;
- }
- cause &= ~handled;
- _splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
- ci->ci_idepth--;
-#ifdef __HAVE_FAST_SOFTINTS
- /* software interrupt */
- ipending &= (MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0);
- if (ipending == 0)
- return;
- _clrsoftintr(ipending);
- softintr_dispatch(ipending);
-#endif
+ if (pending & MIPS_INT_MASK_4) {
+ /* ICU interrupts */
+ intr_handle(&cpu_intrtab[4]);
+ }
+ (void)splhigh();
+ }
}
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