[src/trunk]: src/sys/dev/pci The GIO master enable bit in STATUS register is ...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/412a83fd11da
branches:  trunk
changeset: 755848:412a83fd11da
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Fri Jun 25 03:47:57 2010 +0000

description:
The GIO master enable bit in STATUS register is not bit 16 but bit 19.
It will fix a problem in the reset sequence on PCI-e chips.

diffstat:

 sys/dev/pci/if_wmreg.h |  4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diffs (18 lines):

diff -r 5a73f0cc35b3 -r 412a83fd11da sys/dev/pci/if_wmreg.h
--- a/sys/dev/pci/if_wmreg.h    Fri Jun 25 03:37:27 2010 +0000
+++ b/sys/dev/pci/if_wmreg.h    Fri Jun 25 03:47:57 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_wmreg.h,v 1.40 2010/03/07 09:05:19 msaitoh Exp $    */
+/*     $NetBSD: if_wmreg.h,v 1.41 2010/06/25 03:47:57 msaitoh Exp $    */
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
@@ -231,7 +231,7 @@
 #define        STATUS_PCIXSPD_66_100  STATUS_PCIXSPD(1)
 #define        STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2)
 #define        STATUS_PCIXSPD_MASK    STATUS_PCIXSPD(3)
-#define        STATUS_GIO_M_ENA (1U << 16)     /* PCIX master enable */
+#define        STATUS_GIO_M_ENA (1U << 19)     /* GIO master enable */
 
 #define        WMREG_EECD      0x0010  /* EEPROM Control Register */
 #define        EECD_SK         (1U << 0)       /* clock */