[src/trunk]: src/sys/arch/x86/acpi Fix and add comments.

[jruoho <jruoho%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/80200c8167c5
branches:  trunk
changeset: 762103:80200c8167c5
user:      jruoho <jruoho%NetBSD.org@localhost>
date:      Tue Feb 15 17:50:46 2011 +0000

description:
Fix and add comments.

diffstat:

 sys/arch/x86/acpi/acpi_cpu_md.c |  21 ++++++++++++++++++---
 1 files changed, 18 insertions(+), 3 deletions(-)

diffs (58 lines):

diff -r c14e77618eb3 -r 80200c8167c5 sys/arch/x86/acpi/acpi_cpu_md.c
--- a/sys/arch/x86/acpi/acpi_cpu_md.c   Tue Feb 15 16:49:54 2011 +0000
+++ b/sys/arch/x86/acpi/acpi_cpu_md.c   Tue Feb 15 17:50:46 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: acpi_cpu_md.c,v 1.38 2011/01/13 03:40:50 jruoho Exp $ */
+/* $NetBSD: acpi_cpu_md.c,v 1.39 2011/02/15 17:50:46 jruoho Exp $ */
 
 /*-
  * Copyright (c) 2010 Jukka Ruohonen <jruohonen%iki.fi@localhost>
@@ -27,7 +27,7 @@
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.38 2011/01/13 03:40:50 jruoho Exp $");
+__KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.39 2011/02/15 17:50:46 jruoho Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -164,6 +164,10 @@
        if ((ci->ci_feat_val[1] & CPUID2_MONITOR) != 0)
                val |= ACPICPU_FLAG_C_FFH;
 
+       /*
+        * By default, assume that the local APIC timer
+        * as well as TSC are stalled during C3 sleep.
+        */
        val |= ACPICPU_FLAG_C_APIC | ACPICPU_FLAG_C_TSC;
 
        switch (cpu_vendor) {
@@ -180,8 +184,19 @@
 
        case CPUVENDOR_INTEL:
 
+               /*
+                * Bus master control and arbitration should be
+                * available on all supported Intel CPUs (to be
+                * sure, this is double-checked later from the
+                * firmware data). These flags imply that it is
+                * not necessary to flush caches before C3 state.
+                */
                val |= ACPICPU_FLAG_C_BM | ACPICPU_FLAG_C_ARB;
 
+               /*
+                * Check if we can use "native", MSR-based,
+                * access. If not, we have to resort to I/O.
+                */
                if ((ci->ci_feat_val[1] & CPUID2_EST) != 0)
                        val |= ACPICPU_FLAG_P_FFH;
 
@@ -503,7 +518,7 @@
         * Fill the P-state structures with MSR addresses that are
         * known to be correct. If we do not know the addresses,
         * leave the values intact. If a vendor uses XPSS, we do
-        * not necessary need to do anything to support new CPUs.
+        * not necessarily need to do anything to support new CPUs.
         */
        while (i < sc->sc_pstate_count) {