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[src/trunk]: src/sys/arch/mips Add separate support for MIPS32R2 and MIPS64R2.
details: https://anonhg.NetBSD.org/src/rev/7383d6e2da06
branches: trunk
changeset: 763250:7383d6e2da06
user: matt <matt%NetBSD.org@localhost>
date: Tue Mar 15 07:39:22 2011 +0000
description:
Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.
diffstat:
sys/arch/mips/conf/files.mips | 14 +-
sys/arch/mips/include/cache.h | 4 +-
sys/arch/mips/include/cpu.h | 73 +++++-
sys/arch/mips/include/cpuregs.h | 41 +++-
sys/arch/mips/include/elf_machdep.h | 4 +-
sys/arch/mips/include/locore.h | 37 +--
sys/arch/mips/mips/cache.c | 18 +-
sys/arch/mips/mips/cpu_exec.c | 21 +-
sys/arch/mips/mips/cpu_subr.c | 44 ++++-
sys/arch/mips/mips/genassym.cf | 5 +-
sys/arch/mips/mips/locore.S | 36 +--
sys/arch/mips/mips/locore_mips3.S | 158 ++++++---------
sys/arch/mips/mips/mips32_subr.S | 4 +-
sys/arch/mips/mips/mips32r2_subr.S | 14 +
sys/arch/mips/mips/mips3_subr.S | 4 +-
sys/arch/mips/mips/mips64_subr.S | 4 +-
sys/arch/mips/mips/mips64r2_subr.S | 14 +
sys/arch/mips/mips/mipsX_subr.S | 354 ++++++++++++++---------------------
sys/arch/mips/mips/mips_emul.c | 6 +-
sys/arch/mips/mips/mips_machdep.c | 223 ++++++++++++++++++++--
sys/arch/mips/mips/trap.c | 55 ++++-
21 files changed, 692 insertions(+), 441 deletions(-)
diffs (truncated from 2670 to 300 lines):
diff -r 15c65751907e -r 7383d6e2da06 sys/arch/mips/conf/files.mips
--- a/sys/arch/mips/conf/files.mips Tue Mar 15 07:33:54 2011 +0000
+++ b/sys/arch/mips/conf/files.mips Tue Mar 15 07:39:22 2011 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.mips,v 1.65 2011/02/20 07:45:46 matt Exp $
+# $NetBSD: files.mips,v 1.66 2011/03/15 07:39:22 matt Exp $
#
defflag opt_cputype.h NOFPU FPEMUL
@@ -8,7 +8,7 @@
MIPS64_XLP MIPS64_XLR MIPS64_XLS
# and the rest...
# MIPS1 MIPS2 MIPS3 MIPS4 MIPS5
- # MIPS32 MIPS64
+ # MIPS32 MIPS32R2 MIPS64 MIPS64R2
# MIPS3_4100
# ENABLE_MIPS_4KB_PAGE
# ENABLE_MIPS_TX3900
@@ -22,10 +22,12 @@
defflag opt_ddb.h MIPS_DDB_WATCH
file arch/mips/mips/locore_mips1.S mips1
-file arch/mips/mips/locore_mips3.S mips3 | mips4 | mips32 | mips64
-file arch/mips/mips/mips3_subr.S mips3 | mips4
+file arch/mips/mips/locore_mips3.S mips3|mips4|mips32|mips64|mips32r2|mips64r2
+file arch/mips/mips/mips3_subr.S mips3|mips4
file arch/mips/mips/mips32_subr.S mips32
+file arch/mips/mips/mips32r2_subr.S mips32r2
file arch/mips/mips/mips64_subr.S mips64
+file arch/mips/mips/mips64r2_subr.S mips64r2
file arch/mips/mips/sigcode.S
file arch/mips/mips/copy.S
file arch/mips/mips/lock_stubs_llsc.S multiprocessor
@@ -55,7 +57,7 @@
file arch/mips/mips/vm_machdep.c
file arch/mips/mips/process_machdep.c
file arch/mips/mips/cpu_exec.c
-file arch/mips/mips/wired_map.c (mips3|mips4|mips32|mips64) & enable_mips3_wired_map
+file arch/mips/mips/wired_map.c (mips3|mips4|mips32|mips32r2|mips64|mips64r2) & enable_mips3_wired_map
file arch/mips/mips/cache.c
file arch/mips/mips/cache_r3k.c mips1
@@ -67,7 +69,7 @@
file arch/mips/mips/cache_r5k.c mips3 | mips4
file arch/mips/mips/cache_r5k_subr.S mips3 | mips4
file arch/mips/mips/cache_r10k.c (mips3|mips4) & enable_mips4_cache_r10k
-file arch/mips/mips/cache_mipsNN.c mips32 | mips64
+file arch/mips/mips/cache_mipsNN.c mips32|mips32r2|mips64|mips64r2
file arch/mips/mips/mips_fputrap.c !nofpu | fpemul
file arch/mips/mips/mips_emul.c
diff -r 15c65751907e -r 7383d6e2da06 sys/arch/mips/include/cache.h
--- a/sys/arch/mips/include/cache.h Tue Mar 15 07:33:54 2011 +0000
+++ b/sys/arch/mips/include/cache.h Tue Mar 15 07:39:22 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.h,v 1.10 2011/02/20 07:45:47 matt Exp $ */
+/* $NetBSD: cache.h,v 1.11 2011/03/15 07:39:22 matt Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -207,7 +207,7 @@
u_int mci_dcache_align_mask;
u_int mci_cache_prefer_mask;
-#if defined(MIPS2) || defined(MIPS3) || defined(MIPS32) || defined(MIPS64)
+#if (MIPS2 + MIPS3 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
u_int mci_cache_alias_mask;
bool mci_cache_virtual_alias;
diff -r 15c65751907e -r 7383d6e2da06 sys/arch/mips/include/cpu.h
--- a/sys/arch/mips/include/cpu.h Tue Mar 15 07:33:54 2011 +0000
+++ b/sys/arch/mips/include/cpu.h Tue Mar 15 07:39:22 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.98 2011/02/20 07:45:47 matt Exp $ */
+/* $NetBSD: cpu.h,v 1.99 2011/03/15 07:39:22 matt Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -153,12 +153,15 @@
#define MIPS64 1
#endif
-#if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0
-#error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified
+#if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0
+#error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, or MIPS64RR2 must be specified
#endif
/* Shortcut for MIPS3 or above defined */
-#if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)
+#if defined(MIPS3) || defined(MIPS4) \
+ || defined(MIPS32) || defined(MIPS32R2) \
+ || defined(MIPS64) || defined(MIPS64R2)
+
#define MIPS3_PLUS 1
#define __HAVE_CPU_COUNTER
#else
@@ -170,14 +173,16 @@
* or if possible, at compile-time.
*/
-#define CPU_ARCH_MIPSx 0 /* XXX unknown */
-#define CPU_ARCH_MIPS1 (1 << 0)
-#define CPU_ARCH_MIPS2 (1 << 1)
-#define CPU_ARCH_MIPS3 (1 << 2)
-#define CPU_ARCH_MIPS4 (1 << 3)
-#define CPU_ARCH_MIPS5 (1 << 4)
-#define CPU_ARCH_MIPS32 (1 << 5)
-#define CPU_ARCH_MIPS64 (1 << 6)
+#define CPU_ARCH_MIPSx 0 /* XXX unknown */
+#define CPU_ARCH_MIPS1 (1 << 0)
+#define CPU_ARCH_MIPS2 (1 << 1)
+#define CPU_ARCH_MIPS3 (1 << 2)
+#define CPU_ARCH_MIPS4 (1 << 3)
+#define CPU_ARCH_MIPS5 (1 << 4)
+#define CPU_ARCH_MIPS32 (1 << 5)
+#define CPU_ARCH_MIPS64 (1 << 6)
+#define CPU_ARCH_MIPS32R2 (1 << 7)
+#define CPU_ARCH_MIPS64R2 (1 << 8)
/* Note: must be kept in sync with -ffixed-?? Makefile.mips. */
#define MIPS_CURLWP $24
@@ -251,14 +256,16 @@
#endif /* !_LOCORE */
-#if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE)
+#if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 1) || defined(_LOCORE)
#if defined(MIPS1)
# define CPUISMIPS3 0
# define CPUIS64BITS 0
# define CPUISMIPS32 0
+# define CPUISMIPS32R2 0
# define CPUISMIPS64 0
+# define CPUISMIPS64R2 0
# define CPUISMIPSNN 0
# define MIPS_HAS_R4K_MMU 0
# define MIPS_HAS_CLOCK 0
@@ -270,7 +277,9 @@
# define CPUISMIPS3 1
# define CPUIS64BITS 1
# define CPUISMIPS32 0
+# define CPUISMIPS32R2 0
# define CPUISMIPS64 0
+# define CPUISMIPS64R2 0
# define CPUISMIPSNN 0
# define MIPS_HAS_R4K_MMU 1
# define MIPS_HAS_CLOCK 1
@@ -290,7 +299,23 @@
# define CPUISMIPS3 1
# define CPUIS64BITS 0
# define CPUISMIPS32 1
+# define CPUISMIPS32R2 0
# define CPUISMIPS64 0
+# define CPUISMIPS64R2 0
+# define CPUISMIPSNN 1
+# define MIPS_HAS_R4K_MMU 1
+# define MIPS_HAS_CLOCK 1
+# define MIPS_HAS_LLSC 1
+# define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
+
+#elif defined(MIPS32R2)
+
+# define CPUISMIPS3 1
+# define CPUIS64BITS 0
+# define CPUISMIPS32 0
+# define CPUISMIPS32R2 1
+# define CPUISMIPS64 0
+# define CPUISMIPS64R2 0
# define CPUISMIPSNN 1
# define MIPS_HAS_R4K_MMU 1
# define MIPS_HAS_CLOCK 1
@@ -302,7 +327,23 @@
# define CPUISMIPS3 1
# define CPUIS64BITS 1
# define CPUISMIPS32 0
+# define CPUISMIPS32R2 0
# define CPUISMIPS64 1
+# define CPUISMIPS64R2 0
+# define CPUISMIPSNN 1
+# define MIPS_HAS_R4K_MMU 1
+# define MIPS_HAS_CLOCK 1
+# define MIPS_HAS_LLSC 1
+# define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0)
+
+#elif defined(MIPS64R2)
+
+# define CPUISMIPS3 1
+# define CPUIS64BITS 1
+# define CPUISMIPS32 0
+# define CPUISMIPS32R2 0
+# define CPUISMIPS64 0
+# define CPUISMIPS64R2 1
# define CPUISMIPSNN 1
# define MIPS_HAS_R4K_MMU 1
# define MIPS_HAS_CLOCK 1
@@ -327,10 +368,12 @@
#define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0)
#define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0)
#define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0)
+#define CPUISMIPS32R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) != 0)
#define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0)
-#define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0)
+#define CPUISMIPS64R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) != 0)
+#define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0)
#define CPUIS64BITS ((mips_options.mips_cpu_arch & \
- (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0)
+ (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0)
#define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3)
diff -r 15c65751907e -r 7383d6e2da06 sys/arch/mips/include/cpuregs.h
--- a/sys/arch/mips/include/cpuregs.h Tue Mar 15 07:33:54 2011 +0000
+++ b/sys/arch/mips/include/cpuregs.h Tue Mar 15 07:39:22 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.81 2011/03/03 18:44:58 matt Exp $ */
+/* $NetBSD: cpuregs.h,v 1.82 2011/03/15 07:39:22 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -132,7 +132,24 @@
#define CCA_CACHEABLE 3 /* cacheable non-coherent */
/* CPU dependent mtc0 hazard hook */
-#define COP0_SYNC /* nothing */
+#if (MIPS32R2 + MIPS64R2) > 0
+# if (MIPS1 + MIPS3 + MIPS32 + MIPS64) == 0
+# define COP0_SYNC sll $0,$0,3 /* EHB */
+# define JR_HB_RA .set push; .set mips32r2; jr.hb ra; nop; .set pop
+# else
+# define COP0_SYNC sll $0,$0,1; sll $0,$0,1; sll $0,$0,3
+# define JR_HB_RA sll $0,$0,1; sll $0,$0,1; jr ra; sll $0,$0,3
+# endif
+#elif (MIPS32 + MIPS64) > 0
+# define COP0_SYNC sll $0,$0,1; sll $0,$0,1; sll $0,$0,1
+# define JR_HB_RA sll $0,$0,1; sll $0,$0,1; jr ra; sll $0,$0,1
+#elif MIPS3 > 0
+# define COP0_SYNC nop; nop; nop
+# define JR_HB_RA nop; nop; jr ra; nop
+#else
+# define COP0_SYNC nop
+# define JR_HB_RA jr ra; nop
+#endif
#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
/*
@@ -249,7 +266,6 @@
#define MIPS3_SR_DIAG_CH 0x00040000
#define MIPS3_SR_DIAG_CE 0x00020000
#define MIPS3_SR_DIAG_PE 0x00010000
-#define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */
#define MIPS3_SR_KX 0x00000080
#define MIPS3_SR_SX 0x00000040
#define MIPS3_SR_UX 0x00000020
@@ -544,6 +560,7 @@
#define MIPS_COP_0_ERROR_PC _(30)
/* MIPS32/64 */
+#define MIPS_COP_0_HWRENA _(7)
#define MIPS_COP_0_OSSCRATCH _(22)
#define MIPS_COP_0_DEBUG _(23)
#define MIPS_COP_0_DEPC _(24)
@@ -706,15 +723,13 @@
/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
-#if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
- && defined(MIPS1) /* XXX simonb must be neater! */
+#if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 && MIPS1 != 0
#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
#define MIPS_TLB_PID MIPS1_TLB_PID
#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
#endif
-#if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
- && !defined(MIPS1) /* XXX simonb must be neater! */
+#if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) != 0 && MIPS1 == 0
#define MIPS_TLB_PID_SHIFT 0
#define MIPS_TLB_PID MIPS3_TLB_PID
#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
@@ -733,6 +748,17 @@
#endif
/*
+ * Bits defined for for the HWREna (CP0 register 7, select 0).
+ */
+#define MIPS_HWRENA_IMPL31 __BIT(31)
+#define MIPS_HWRENA_IMPL30 __BIT(30)
+#define MIPS_HWRENA_UL __BIT(29) /* Userlocal */
+#define MIPS_HWRENA_CCRES __BIT(3)
+#define MIPS_HWRENA_CC __BIT(2)
+#define MIPS_HWRENA_SYNCI_STEP __BIT(1)
+#define MIPS_HWRENA_CPUNUM __BIT(0)
+
+/*
* Hints for the prefetch instruction
*/
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