[src/trunk]: src/sys/arch/arm implement arm32_pmap_flags() to allow mappings ...

[macallan <macallan%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/80b0b028a770
branches:  trunk
changeset: 762778:80b0b028a770
user:      macallan <macallan%NetBSD.org@localhost>
date:      Mon Feb 28 10:03:49 2011 +0000

description:
implement arm32_pmap_flags() to allow mappings with write buffering enabled,
mostly for video memory
Tested on shark

diffstat:

 sys/arch/arm/arm32/pmap.c         |  42 +++++++++++++++++++++++++++++++++++---
 sys/arch/arm/include/arm32/pmap.h |  10 ++++++++-
 2 files changed, 47 insertions(+), 5 deletions(-)

diffs (164 lines):

diff -r 16c1cba57e1a -r 80b0b028a770 sys/arch/arm/arm32/pmap.c
--- a/sys/arch/arm/arm32/pmap.c Mon Feb 28 09:10:28 2011 +0000
+++ b/sys/arch/arm/arm32/pmap.c Mon Feb 28 10:03:49 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.219 2010/11/12 07:59:25 uebayasi Exp $      */
+/*     $NetBSD: pmap.c,v 1.220 2011/02/28 10:03:49 macallan Exp $      */
 
 /*
  * Copyright 2003 Wasabi Systems, Inc.
@@ -211,7 +211,7 @@
 #include <machine/param.h>
 #include <arm/arm32/katelib.h>
 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.219 2010/11/12 07:59:25 uebayasi Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.220 2011/02/28 10:03:49 macallan Exp $");
 
 #ifdef PMAP_DEBUG
 
@@ -2745,6 +2745,16 @@
        return (pm);
 }
 
+u_int
+arm32_mmap_flags(paddr_t pa)
+{
+       /*
+        * the upper 8 bits in pmap_enter()'s flags are reserved for MD stuff
+        * and we're using the upper bits in page numbers to pass flags around
+        * so we might as well use the same bits
+        */
+       return (u_int)pa & PMAP_MD_MASK;
+}
 /*
  * int pmap_enter(pmap_t pm, vaddr_t va, paddr_t pa, vm_prot_t prot,
  *      u_int flags)
@@ -2953,9 +2963,12 @@
                /*
                 * Make sure the vector table is mapped cacheable
                 */
-               if (pm != pmap_kernel() && va == vector_page)
+               if ((pm != pmap_kernel() && va == vector_page) ||
+                   (flags & ARM32_MMAP_CACHEABLE)) {
                        npte |= pte_l2_s_cache_mode;
-
+               } else if (flags & ARM32_MMAP_WRITECOMBINE) {
+                       npte |= pte_l2_s_wc_mode;
+               }
                if (opg) {
                        /*
                         * Looks like there's an existing 'managed' mapping
@@ -5917,14 +5930,17 @@
  */
 
 pt_entry_t     pte_l1_s_cache_mode;
+pt_entry_t     pte_l1_s_wc_mode;
 pt_entry_t     pte_l1_s_cache_mode_pt;
 pt_entry_t     pte_l1_s_cache_mask;
 
 pt_entry_t     pte_l2_l_cache_mode;
+pt_entry_t     pte_l2_l_wc_mode;
 pt_entry_t     pte_l2_l_cache_mode_pt;
 pt_entry_t     pte_l2_l_cache_mask;
 
 pt_entry_t     pte_l2_s_cache_mode;
+pt_entry_t     pte_l2_s_wc_mode;
 pt_entry_t     pte_l2_s_cache_mode_pt;
 pt_entry_t     pte_l2_s_cache_mask;
 
@@ -5956,12 +5972,15 @@
 {
 
        pte_l1_s_cache_mode = L1_S_B|L1_S_C;
+       pte_l1_s_wc_mode = L1_S_B;
        pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
 
        pte_l2_l_cache_mode = L2_B|L2_C;
+       pte_l2_l_wc_mode = L2_B;
        pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
 
        pte_l2_s_cache_mode = L2_B|L2_C;
+       pte_l2_s_wc_mode = L2_B;
        pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
 
        /*
@@ -6040,6 +6059,10 @@
        pte_l2_l_cache_mode = L2_C;
        pte_l2_s_cache_mode = L2_C;
 
+       pte_l1_s_wc_mode = L1_S_B;
+       pte_l2_l_wc_mode = L2_B;
+       pte_l2_s_wc_mode = L2_B;
+
        pte_l1_s_cache_mode_pt = L1_S_C;
        pte_l2_l_cache_mode_pt = L2_C;
        pte_l2_s_cache_mode_pt = L2_C;
@@ -6062,6 +6085,10 @@
        pte_l2_l_cache_mode = L2_B | L2_C;
        pte_l2_s_cache_mode = L2_B | L2_C;
 
+       pte_l1_s_cache_mode = L1_S_B;
+       pte_l2_l_cache_mode = L2_B;
+       pte_l2_s_cache_mode = L2_B;
+
        pte_l1_s_cache_mode_pt = L1_S_C;
        pte_l2_l_cache_mode_pt = L2_C;
        pte_l2_s_cache_mode_pt = L2_C;
@@ -6084,6 +6111,10 @@
        pte_l2_l_cache_mode = L2_C;
        pte_l2_s_cache_mode = L2_C;
 
+       pte_l1_s_wc_mode = L1_S_B;
+       pte_l2_l_wc_mode = L2_B;
+       pte_l2_s_wc_mode = L2_B;
+
        pte_l1_s_cache_mode_pt = L1_S_C;
        pte_l2_l_cache_mode_pt = L2_C;
        pte_l2_s_cache_mode_pt = L2_C;
@@ -6123,12 +6154,15 @@
        int write_through = 0;
 
        pte_l1_s_cache_mode = L1_S_B|L1_S_C;
+       pte_l1_s_wc_mode = L1_S_B;
        pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
 
        pte_l2_l_cache_mode = L2_B|L2_C;
+       pte_l2_l_wc_mode = L2_B;
        pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
 
        pte_l2_s_cache_mode = L2_B|L2_C;
+       pte_l2_s_wc_mode = L2_B;
        pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
 
        pte_l1_s_cache_mode_pt = L1_S_C;
diff -r 16c1cba57e1a -r 80b0b028a770 sys/arch/arm/include/arm32/pmap.h
--- a/sys/arch/arm/include/arm32/pmap.h Mon Feb 28 09:10:28 2011 +0000
+++ b/sys/arch/arm/include/arm32/pmap.h Mon Feb 28 10:03:49 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.h,v 1.97 2010/11/14 13:33:21 uebayasi Exp $       */
+/*     $NetBSD: pmap.h,v 1.98 2011/02/28 10:03:49 macallan Exp $       */
 
 /*
  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -278,6 +278,10 @@
 #define        pmap_copy(dp, sp, da, l, sa)    /* nothing */
 
 #define pmap_phys_address(ppn)         (arm_ptob((ppn)))
+u_int arm32_mmap_flags(paddr_t);
+#define ARM32_MMAP_WRITECOMBINE        0x40000000
+#define ARM32_MMAP_CACHEABLE           0x20000000
+#define pmap_mmap_flags(ppn)                   arm32_mmap_flags(ppn)
 
 /*
  * Functions that we need to export
@@ -500,6 +504,10 @@
 extern pt_entry_t              pte_l2_l_cache_mode_pt;
 extern pt_entry_t              pte_l2_s_cache_mode_pt;
 
+extern pt_entry_t              pte_l1_s_wc_mode;
+extern pt_entry_t              pte_l2_l_wc_mode;
+extern pt_entry_t              pte_l2_s_wc_mode;
+
 extern pt_entry_t              pte_l1_s_prot_u;
 extern pt_entry_t              pte_l1_s_prot_w;
 extern pt_entry_t              pte_l1_s_prot_ro;