[src/trunk]: src/sys/arch/sparc64/sparc64 first steps towards fujitsu SPARC64...

[mrg <mrg%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/c7b7e93c8af1
branches:  trunk
changeset: 764923:c7b7e93c8af1
user:      mrg <mrg%NetBSD.org@localhost>
date:      Thu May 12 05:42:42 2011 +0000

description:
first steps towards fujitsu SPARC64 support:

- sun4us and sun4v systems don't need dcache_flush_page or
  blast_icache ops

diffstat:

 sys/arch/sparc64/sparc64/cache.h |  16 +++++++++++++---
 1 files changed, 13 insertions(+), 3 deletions(-)

diffs (42 lines):

diff -r c96131d40107 -r c7b7e93c8af1 sys/arch/sparc64/sparc64/cache.h
--- a/sys/arch/sparc64/sparc64/cache.h  Thu May 12 05:42:22 2011 +0000
+++ b/sys/arch/sparc64/sparc64/cache.h  Thu May 12 05:42:42 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.h,v 1.18 2010/03/28 05:24:00 mrg Exp $ */
+/*     $NetBSD: cache.h,v 1.19 2011/05/12 05:42:42 mrg Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -93,6 +93,8 @@
 static __inline__ void
 dcache_flush_page(paddr_t pa)
 {
+       if (CPU_ISSUN4US || CPU_ISSUN4V)
+               return;
        if (CPU_IS_USIII_UP())
                dcache_flush_page_usiii(pa);
        else
@@ -111,6 +113,8 @@
 static __inline__ void
 blast_icache(void)
 {
+       if (CPU_ISSUN4US || CPU_ISSUN4V)
+               return;
        if (CPU_IS_USIII_UP())
                blast_icache_usiii();
        else
@@ -154,6 +158,12 @@
 #define        tlb_flush_pte(va,pm)            sp_tlb_flush_pte(va, (pm)->pm_ctx[0])
 #define        dcache_flush_page_all(pa)       dcache_flush_page(pa)
 #define        dcache_flush_page_cpuset(pa,cs) dcache_flush_page(pa)
-#define        blast_dcache()                  sp_blast_dcache(dcache_size, \
-                                                       dcache_line_size)
+
+static __inline__ void
+blast_dcache(void)
+{
+       if (CPU_ISSUN4US || CPU_ISSUN4V)
+               return;
+       sp_blast_dcache(dcache_size, dcache_line_size);
+}
 #endif