[src/trunk]: src/sys Finish cleaning up pchb from recent change.

[jakllsch <jakllsch%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/1e719f9da7ad
branches:  trunk
changeset: 756554:1e719f9da7ad
user:      jakllsch <jakllsch%NetBSD.org@localhost>
date:      Fri Jul 23 02:23:58 2010 +0000

description:
Finish cleaning up pchb from recent change.
Use fewer magic numbers in ichlpcib.
Slightly improve style conformance.
Update paths in cpp re-inclusion guards.

diffstat:

 sys/arch/x86/pci/ichlpcib.c |  18 ++++++++++--------
 sys/arch/x86/pci/pchbvar.h  |  14 ++++----------
 sys/dev/ic/i82801lpcreg.h   |  12 +++++++-----
 3 files changed, 21 insertions(+), 23 deletions(-)

diffs (121 lines):

diff -r fa6f445ac31f -r 1e719f9da7ad sys/arch/x86/pci/ichlpcib.c
--- a/sys/arch/x86/pci/ichlpcib.c       Fri Jul 23 00:50:39 2010 +0000
+++ b/sys/arch/x86/pci/ichlpcib.c       Fri Jul 23 02:23:58 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ichlpcib.c,v 1.25 2010/07/23 00:43:21 jakllsch Exp $   */
+/*     $NetBSD: ichlpcib.c,v 1.26 2010/07/23 02:23:58 jakllsch Exp $   */
 
 /*-
  * Copyright (c) 2004 The NetBSD Foundation, Inc.
@@ -39,7 +39,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.25 2010/07/23 00:43:21 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.26 2010/07/23 02:23:58 jakllsch Exp $");
 
 #include <sys/types.h>
 #include <sys/param.h>
@@ -1241,9 +1241,10 @@
 static void
 lpcib_fwh_configure(device_t self)
 {
-       struct lpcib_softc *sc = device_private(self);
+       struct lpcib_softc *sc;
+       pcireg_t pr;
 
-       pcireg_t pr;
+       sc = device_private(self);
 
        if (sc->sc_has_rcba) {
                /*
@@ -1254,15 +1255,16 @@
        } else {
                /* Enable FWH write to identify FWH. */
                pr = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag,
-                   0x4c);
+                   LPCIB_PCI_BIOS_CNTL);
                pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag,
-                   0x4c, pr|__BIT(16));
+                   LPCIB_PCI_BIOS_CNTL, pr|LPCIB_PCI_BIOS_CNTL_BWE);
        }
 
        sc->sc_fwhbus = config_found_ia(self, "fwhichbus", NULL, NULL);
 
-       /* disable write */
-       pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 0x4c, pr);
+       /* restore previous write enable setting */
+       pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag,
+           LPCIB_PCI_BIOS_CNTL, pr);
 }
 
 static int
diff -r fa6f445ac31f -r 1e719f9da7ad sys/arch/x86/pci/pchbvar.h
--- a/sys/arch/x86/pci/pchbvar.h        Fri Jul 23 00:50:39 2010 +0000
+++ b/sys/arch/x86/pci/pchbvar.h        Fri Jul 23 02:23:58 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pchbvar.h,v 1.6 2010/07/23 00:43:21 jakllsch Exp $     */
+/*     $NetBSD: pchbvar.h,v 1.7 2010/07/23 02:23:58 jakllsch Exp $     */
 
 /*-
  * Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -29,11 +29,8 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef _I386_PCI_PCHBVAR_H_
-#define        _I386_PCI_PCHBVAR_H_
-
-#include <sys/callout.h>
-#include <sys/rnd.h>
+#ifndef _X86_PCI_PCHBVAR_H_
+#define _X86_PCI_PCHBVAR_H_
 
 struct pchb_softc {
        device_t sc_dev;
@@ -44,7 +41,4 @@
        pcireg_t sc_pciconfext[48];
 };
 
-void   pchb_attach_rnd(struct pchb_softc *, struct pci_attach_args *);
-void   pchb_detach_rnd(struct pchb_softc *);
-
-#endif /* _I386_PCI_PCHBVAR_H_ */
+#endif /* _X86_PCI_PCHBVAR_H_ */
diff -r fa6f445ac31f -r 1e719f9da7ad sys/dev/ic/i82801lpcreg.h
--- a/sys/dev/ic/i82801lpcreg.h Fri Jul 23 00:50:39 2010 +0000
+++ b/sys/dev/ic/i82801lpcreg.h Fri Jul 23 02:23:58 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: i82801lpcreg.h,v 1.10 2009/09/27 17:55:32 jakllsch Exp $       */
+/*     $NetBSD: i82801lpcreg.h,v 1.11 2010/07/23 02:23:58 jakllsch Exp $       */
 
 /*-
  * Copyright (c) 2004 The NetBSD Foundation, Inc.
@@ -34,8 +34,8 @@
  *   register definitions.
  */
 
-#ifndef _DEV_IC_I82801LPGREG_H_
-#define _DEV_IC_I82801LPGREG_H_
+#ifndef _DEV_IC_I82801LPCREG_H_
+#define _DEV_IC_I82801LPCREG_H_
 /*
  * PCI configuration registers
  */
@@ -45,7 +45,9 @@
 /* GPIO config registers ICH6+ */
 #define LPCIB_PCI_GPIO_BASE_ICH6       0x48
 #define LPCIB_PCI_GPIO_CNTL_ICH6       0x4c
-#define LPCIB_PCI_BIOS_CNTL    0x4e
+#define LPCIB_PCI_BIOS_CNTL    0x4c /* actually 0x4e */
+#define LPCIB_PCI_BIOS_CNTL_BWE        (0x0001 << 16) /* write enable */
+#define LPCIB_PCI_BIOS_CNTL_BLE        (0x0002 << 16) /* lock enable */
 #define LPCIB_PCI_TCO_CNTL     0x54
 /* GPIO config registers ICH0-ICH5 */
 #define LPCIB_PCI_GPIO_BASE    0x58
@@ -297,4 +299,4 @@
 #define LPCIB_TCOTIMER_MAX_TICK        0x3f    /* 39 seconds max */
 #define LPCIB_TCOTIMER2_MAX_TICK       0x265   /* 613 seconds max */
 
-#endif /*  _DEV_IC_I82801LPGREG_H_ */
+#endif /*  _DEV_IC_I82801LPCREG_H_ */