[src/trunk]: src/sys/dev Fixes from PR kern/44395 Masanori Kanaoka:

[cegger <cegger%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/4bd580207e52
branches:  trunk
changeset: 761250:4bd580207e52
user:      cegger <cegger%NetBSD.org@localhost>
date:      Sat Jan 22 08:13:47 2011 +0000

description:
Fixes from PR kern/44395 Masanori Kanaoka:
- Fix register address in ale_phy_reset(). from linux
- Fix mask value in ale_stop_mac().
- Fix multicast handling. from openbsd
- Fix phy reset handling.

diffstat:

 sys/dev/mii/atphy.c  |  18 +++++++++++-------
 sys/dev/pci/if_ale.c |  12 ++++++------
 2 files changed, 17 insertions(+), 13 deletions(-)

diffs (119 lines):

diff -r fe2f68b9b28b -r 4bd580207e52 sys/dev/mii/atphy.c
--- a/sys/dev/mii/atphy.c       Sat Jan 22 07:38:51 2011 +0000
+++ b/sys/dev/mii/atphy.c       Sat Jan 22 08:13:47 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: atphy.c,v 1.7 2010/12/11 18:10:16 matt Exp $ */
+/*     $NetBSD: atphy.c,v 1.8 2011/01/22 08:13:47 cegger Exp $ */
 /*     $OpenBSD: atphy.c,v 1.1 2008/09/25 20:47:16 brad Exp $  */
 
 /*-
@@ -33,7 +33,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.7 2010/12/11 18:10:16 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: atphy.c,v 1.8 2011/01/22 08:13:47 cegger Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -118,6 +118,7 @@
        struct mii_attach_args *ma = aux;
        struct mii_data *mii = ma->mii_data;
        const struct mii_phydesc *mpd;
+       uint16_t bmsr;
 
        mpd = mii_phy_match(ma, etphys);
        aprint_naive(": Media interface\n");
@@ -135,7 +136,8 @@
 
        PHY_RESET(sc);
 
-       sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
+       bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
+       sc->mii_capabilities = bmsr & ma->mii_capmask;
        if (sc->mii_capabilities & BMSR_EXTSTAT)
                sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 
@@ -220,8 +222,7 @@
                /*
                 * Reset the PHY so all changes take effect.
                 */
-               PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |
-                   BMCR_STARTNEG);
+               PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG);
 done:
                break;
 
@@ -364,8 +365,11 @@
        reg |= ATPHY_SCR_POLARITY_REVERSAL;
        PHY_WRITE(sc, ATPHY_SCR, reg);
 
+       atphy_mii_phy_auto(sc);
+
        /* Workaround F1 bug to reset phy. */
-       atphy_mii_phy_auto(sc);
+       reg = PHY_READ(sc, MII_BMCR) | BMCR_RESET;
+       PHY_WRITE(sc, MII_BMCR, reg);
 
        for (i = 0; i < 1000; i++) {
                DELAY(1);
@@ -386,7 +390,7 @@
        if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX))
                PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
                    GTCR_ADV_1000THDX);
-       PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
+       PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
 
        return EJUSTRETURN;
 }
diff -r fe2f68b9b28b -r 4bd580207e52 sys/dev/pci/if_ale.c
--- a/sys/dev/pci/if_ale.c      Sat Jan 22 07:38:51 2011 +0000
+++ b/sys/dev/pci/if_ale.c      Sat Jan 22 08:13:47 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_ale.c,v 1.12 2010/07/20 09:17:24 cegger Exp $       */
+/*     $NetBSD: if_ale.c,v 1.13 2011/01/22 08:13:47 cegger Exp $       */
 
 /*-
  * Copyright (c) 2008, Pyun YongHyeon <yongari%FreeBSD.org@localhost>
@@ -32,7 +32,7 @@
 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.12 2010/07/20 09:17:24 cegger Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.13 2011/01/22 08:13:47 cegger Exp $");
 
 #include "vlan.h"
 
@@ -367,12 +367,12 @@
        ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr,
            ATPHY_DBG_ADDR, 0x04);
        ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr,
-           ATPHY_DBG_ADDR, 0x8BBB);
+           ATPHY_DBG_DATA, 0x8BBB);
        /* 10BT center tap voltage. */
        ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr,
            ATPHY_DBG_ADDR, 0x05);
        ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr,
-           ATPHY_DBG_ADDR, 0x2C46);
+           ATPHY_DBG_DATA, 0x2C46);
 
 #undef ATPHY_DBG_ADDR
 #undef ATPHY_DBG_DATA
@@ -1910,7 +1910,7 @@
 
        reg = CSR_READ_4(sc, ALE_MAC_CFG);
        if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
-               reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
+               reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
                CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
        }
 
@@ -2015,7 +2015,7 @@
 
                ETHER_FIRST_MULTI(step, ec, enm);
                while (enm != NULL) {
-                       crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
+                       crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
                        mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
                        ETHER_NEXT_MULTI(step, enm);
                }