[src/trunk]: src/sys/arch/sparc64/include Move ASRs macro to more appropriate...

[nakayama <nakayama%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/73a6feac4ae2
branches:  trunk
changeset: 782601:73a6feac4ae2
user:      nakayama <nakayama%NetBSD.org@localhost>
date:      Thu Nov 08 16:30:12 2012 +0000

description:
Move ASRs macro to more appropriate header.
While there remove useless macro.

diffstat:

 sys/arch/sparc64/include/ctlreg.h |  28 +---------------------------
 sys/arch/sparc64/include/psl.h    |  16 +++++++++++++++-
 2 files changed, 16 insertions(+), 28 deletions(-)

diffs (72 lines):

diff -r 28d5b9e3b9dd -r 73a6feac4ae2 sys/arch/sparc64/include/ctlreg.h
--- a/sys/arch/sparc64/include/ctlreg.h Thu Nov 08 15:39:29 2012 +0000
+++ b/sys/arch/sparc64/include/ctlreg.h Thu Nov 08 16:30:12 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ctlreg.h,v 1.57 2012/11/08 00:34:37 macallan Exp $ */
+/*     $NetBSD: ctlreg.h,v 1.58 2012/11/08 16:30:12 nakayama Exp $ */
 
 /*
  * Copyright (c) 1996-2002 Eduardo Horvath
@@ -410,32 +410,6 @@
 #define        IRDR_3H         0x70    /* unimplemented */
 #define        IRDR_3L         0x78    /* unimplemented */
 
-/* SOFTINT ASRs */
-#define        SET_SOFTINT     %asr20  /* Sets these bits */
-#define        CLEAR_SOFTINT   %asr21  /* Clears these bits */
-#define        SOFTINT         %asr22  /* Reads the register */
-#define        TICK_CMPR       %asr23
-#define        STICK           %asr24
-#define        STICK_CMPR      %asr25
-
-#define        TICK_INT        0x01    /* level-14 clock tick */
-#define        SOFTINT1        (0x1<<1)
-#define        SOFTINT2        (0x1<<2)
-#define        SOFTINT3        (0x1<<3)
-#define        SOFTINT4        (0x1<<4)
-#define        SOFTINT5        (0x1<<5)
-#define        SOFTINT6        (0x1<<6)
-#define        SOFTINT7        (0x1<<7)
-#define        SOFTINT8        (0x1<<8)
-#define        SOFTINT9        (0x1<<9)
-#define        SOFTINT10       (0x1<<10)
-#define        SOFTINT11       (0x1<<11)
-#define        SOFTINT12       (0x1<<12)
-#define        SOFTINT13       (0x1<<13)
-#define        SOFTINT14       (0x1<<14)
-#define        SOFTINT15       (0x1<<15)
-#define        STICK_INTR      (0x1<<16)       /* system tick */
-
 /* Interrupt Dispatch -- usually reserved for cross-calls */
 #define        ASR_IDSR        0x48 /* Interrupt dispatch status reg */
 #define        IDSR            0x00
diff -r 28d5b9e3b9dd -r 73a6feac4ae2 sys/arch/sparc64/include/psl.h
--- a/sys/arch/sparc64/include/psl.h    Thu Nov 08 15:39:29 2012 +0000
+++ b/sys/arch/sparc64/include/psl.h    Thu Nov 08 16:30:12 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: psl.h,v 1.50 2012/11/08 00:34:37 macallan Exp $ */
+/*     $NetBSD: psl.h,v 1.51 2012/11/08 16:30:12 nakayama Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -264,6 +264,20 @@
 
 #define CWP            0x01f
 
+/*
+ * UltraSPARC Ancillary State Registers
+ */
+#define SET_SOFTINT    %asr20  /* Set Software Interrupt register bits */
+#define CLEAR_SOFTINT  %asr21  /* Clear Software Interrupt register bits */
+#define SOFTINT                %asr22  /* Software Interrupt register */
+#define TICK_CMPR      %asr23  /* TICK Compare register */
+#define STICK          %asr24  /* STICK register */
+#define STICK_CMPR     %asr25  /* STICK Compare register */
+
+/* SOFTINT bit descriptions */
+#define TICK_INT       0x01            /* CPU clock timer interrupt */
+#define STICK_INT      (0x1<<16)       /* system clock timer interrupt */
+
 /* 64-byte alignment -- this seems the best place to put this. */
 #define SPARC64_BLOCK_SIZE     64
 #define SPARC64_BLOCK_ALIGN    0x3f