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[src/netbsd-6]: src/sys/dev Apply patch, requested by msaitoh in ticket #983:
details: https://anonhg.NetBSD.org/src/rev/4a8eea1f421c
branches: netbsd-6
changeset: 776497:4a8eea1f421c
user: bouyer <bouyer%NetBSD.org@localhost>
date: Sun Nov 17 18:24:05 2013 +0000
description:
Apply patch, requested by msaitoh in ticket #983:
sys/dev/mii/brgphy.c 1.68 via patch
sys/dev/pci/if_bge.c 1.260-1.262 via patch
sys/dev/pci/if_bgereg.h 1.85-1.86 via patch
sys/dev/pci/if_bgevar.h 1.17 via patch
Set maximum read byte count to 2048 for PCI-X BCM5703/5704 devices.
For PCI-X BCM5704, set maximum outstanding split transactions to 0.
Same as Linux tg3 and FreeBSD (part of FreeBSD r204978).
Add 40bit DMA bug workaround(BGEF_40BIT_BUG) from FreeBSD
(part of r199670). This workaround is for 5714/5715 controllers and
is not actually a MAC controller bug but an issue with the embedded
PCIe to PCI-X bridge in the device. This change
uses bus_dmatag_subregion(), so this workaround won't work on some
archs which doesn't support bus_dmatag_subregion().
diffstat:
sys/dev/mii/brgphy.c | 8 +-
sys/dev/pci/if_bge.c | 269 +++++++++++++++++++++++++++--------------------
sys/dev/pci/if_bgereg.h | 70 ++++++-----
sys/dev/pci/if_bgevar.h | 3 +-
4 files changed, 198 insertions(+), 152 deletions(-)
diffs (truncated from 921 to 300 lines):
diff -r f7178977df9e -r 4a8eea1f421c sys/dev/mii/brgphy.c
--- a/sys/dev/mii/brgphy.c Sun Nov 17 18:19:45 2013 +0000
+++ b/sys/dev/mii/brgphy.c Sun Nov 17 18:24:05 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: brgphy.c,v 1.59.8.2 2013/09/07 16:39:32 bouyer Exp $ */
+/* $NetBSD: brgphy.c,v 1.59.8.3 2013/11/17 18:24:05 bouyer Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
@@ -62,7 +62,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.59.8.2 2013/09/07 16:39:32 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.59.8.3 2013/11/17 18:24:05 bouyer Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -734,11 +734,11 @@
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
}
- if (bsc->sc_phyflags & BGE_PHY_CRC_BUG)
+ if (bsc->sc_phyflags & BGEPHYF_CRC_BUG)
brgphy_crc_bug(sc);
/* Set Jumbo frame settings in the PHY. */
- if (bsc->sc_phyflags & BGE_JUMBO_CAPABLE)
+ if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE)
brgphy_jumbo_settings(sc);
/* Adjust output voltage */
diff -r f7178977df9e -r 4a8eea1f421c sys/dev/pci/if_bge.c
--- a/sys/dev/pci/if_bge.c Sun Nov 17 18:19:45 2013 +0000
+++ b/sys/dev/pci/if_bge.c Sun Nov 17 18:24:05 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_bge.c,v 1.200.2.2 2013/09/07 16:39:32 bouyer Exp $ */
+/* $NetBSD: if_bge.c,v 1.200.2.3 2013/11/17 18:24:05 bouyer Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
@@ -79,7 +79,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.200.2.2 2013/09/07 16:39:32 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.200.2.3 2013/11/17 18:24:05 bouyer Exp $");
#include "vlan.h"
@@ -673,15 +673,15 @@
NULL },
};
-#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE)
-#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY)
-#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS)
-#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY)
-#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS)
-#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS)
-#define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGE_57765_FAMILY)
-#define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS)
-#define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS)
+#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGEF_JUMBO_CAPABLE)
+#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGEF_5700_FAMILY)
+#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGEF_5705_PLUS)
+#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGEF_5714_FAMILY)
+#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGEF_575X_PLUS)
+#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGEF_5755_PLUS)
+#define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags & BGEF_57765_FAMILY)
+#define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGEF_57765_PLUS)
+#define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGEF_5717_PLUS)
static const struct bge_revision {
uint32_t br_chipid;
@@ -1743,7 +1743,7 @@
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
m_new->m_data = m_new->m_ext.ext_buf;
}
- if (!(sc->bge_flags & BGE_RX_ALIGNBUG))
+ if (!(sc->bge_flags & BGEF_RX_ALIGNBUG))
m_adj(m_new, ETHER_ALIGN);
if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new,
BUS_DMA_READ|BUS_DMA_NOWAIT))
@@ -1804,7 +1804,7 @@
buf = m_new->m_data = m_new->m_ext.ext_buf;
m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
}
- if (!(sc->bge_flags & BGE_RX_ALIGNBUG))
+ if (!(sc->bge_flags & BGEF_RX_ALIGNBUG))
m_adj(m_new, ETHER_ALIGN);
bus_dmamap_sync(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map,
mtod(m_new, char *) - (char *)sc->bge_cdata.bge_jumbo_buf, BGE_JLEN,
@@ -1837,7 +1837,7 @@
{
int i;
- if (sc->bge_flags & BGE_RXRING_VALID)
+ if (sc->bge_flags & BGEF_RXRING_VALID)
return 0;
for (i = 0; i < BGE_SSLOTS; i++) {
@@ -1848,7 +1848,7 @@
sc->bge_std = i - 1;
bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
- sc->bge_flags |= BGE_RXRING_VALID;
+ sc->bge_flags |= BGEF_RXRING_VALID;
return 0;
}
@@ -1858,7 +1858,7 @@
{
int i;
- if (!(sc->bge_flags & BGE_RXRING_VALID))
+ if (!(sc->bge_flags & BGEF_RXRING_VALID))
return;
for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
@@ -1872,7 +1872,7 @@
sizeof(struct bge_rx_bd));
}
- sc->bge_flags &= ~BGE_RXRING_VALID;
+ sc->bge_flags &= ~BGEF_RXRING_VALID;
}
static int
@@ -1881,7 +1881,7 @@
int i;
volatile struct bge_rcb *rcb;
- if (sc->bge_flags & BGE_JUMBO_RXRING_VALID)
+ if (sc->bge_flags & BGEF_JUMBO_RXRING_VALID)
return 0;
for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
@@ -1890,7 +1890,7 @@
}
sc->bge_jumbo = i - 1;
- sc->bge_flags |= BGE_JUMBO_RXRING_VALID;
+ sc->bge_flags |= BGEF_JUMBO_RXRING_VALID;
rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
rcb->bge_maxlen_flags = 0;
@@ -1906,7 +1906,7 @@
{
int i;
- if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID))
+ if (!(sc->bge_flags & BGEF_JUMBO_RXRING_VALID))
return;
for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
@@ -1918,7 +1918,7 @@
sizeof(struct bge_rx_bd));
}
- sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID;
+ sc->bge_flags &= ~BGEF_JUMBO_RXRING_VALID;
}
static void
@@ -1927,7 +1927,7 @@
int i;
struct txdmamap_pool_entry *dma;
- if (!(sc->bge_flags & BGE_TXRING_VALID))
+ if (!(sc->bge_flags & BGEF_TXRING_VALID))
return;
for (i = 0; i < BGE_TX_RING_CNT; i++) {
@@ -1948,7 +1948,7 @@
free(dma, M_DEVBUF);
}
- sc->bge_flags &= ~BGE_TXRING_VALID;
+ sc->bge_flags &= ~BGEF_TXRING_VALID;
}
static int
@@ -1960,7 +1960,7 @@
bus_size_t maxsegsz;
struct txdmamap_pool_entry *dma;
- if (sc->bge_flags & BGE_TXRING_VALID)
+ if (sc->bge_flags & BGEF_TXRING_VALID)
return 0;
sc->bge_txcnt = 0;
@@ -2006,7 +2006,7 @@
SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
}
- sc->bge_flags |= BGE_TXRING_VALID;
+ sc->bge_flags |= BGEF_TXRING_VALID;
return 0;
}
@@ -2178,7 +2178,7 @@
aprint_error_dev(sc->bge_dev, "reset timed out\n");
return -1;
}
- } else if ((sc->bge_flags & BGE_NO_EEPROM) == 0) {
+ } else if ((sc->bge_flags & BGEF_NO_EEPROM) == 0) {
/*
* Poll the value location we just wrote until
* we see the 1's complement of the magic number.
@@ -2349,7 +2349,7 @@
/* Set up the PCI DMA control register. */
dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
- if (sc->bge_flags & BGE_PCIE) {
+ if (sc->bge_flags & BGEF_PCIE) {
/* Read watermark not used, 128 bytes for write. */
DPRINTFN(4, ("(%s: PCI-Express DMA setting)\n",
device_xname(sc->bge_dev)));
@@ -2357,7 +2357,7 @@
dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
else
dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
- } else if (sc->bge_flags & BGE_PCIX) {
+ } else if (sc->bge_flags & BGEF_PCIX) {
DPRINTFN(4, ("(:%s: PCI-X DMA setting)\n",
device_xname(sc->bge_dev)));
/* PCI-X bus */
@@ -2979,9 +2979,9 @@
BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
BGE_MACMODE_FRMHDR_DMA_ENB;
- if (sc->bge_flags & BGE_PHY_FIBER_TBI)
+ if (sc->bge_flags & BGEF_FIBER_TBI)
val |= BGE_PORTMODE_TBI;
- else if (sc->bge_flags & BGE_PHY_FIBER_MII)
+ else if (sc->bge_flags & BGEF_FIBER_MII)
val |= BGE_PORTMODE_GMII;
else
val |= BGE_PORTMODE_MII;
@@ -3038,13 +3038,13 @@
BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
- if (sc->bge_flags & BGE_PCIE)
+ if (sc->bge_flags & BGEF_PCIE)
val |= BGE_RDMAMODE_FIFO_LONG_BURST;
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) {
if (ifp->if_mtu <= ETHERMTU)
val |= BGE_RDMAMODE_JMB_2K_MMRR;
}
- if (sc->bge_flags & BGE_TSO)
+ if (sc->bge_flags & BGEF_TSO)
val |= BGE_RDMAMODE_TSO4_ENABLE;
if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
@@ -3134,7 +3134,7 @@
/* 5718 step 60, 57XX step 90 */
/* Turn on send data initiator state machine */
- if (sc->bge_flags & BGE_TSO) {
+ if (sc->bge_flags & BGEF_TSO) {
/* XXX: magic value from Linux driver */
CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
BGE_SDIMODE_HW_LSO_PRE_DMA);
@@ -3165,7 +3165,7 @@
* Enable attention when the link has changed state for
* devices that use auto polling.
*/
- if (sc->bge_flags & BGE_PHY_FIBER_TBI) {
+ if (sc->bge_flags & BGEF_FIBER_TBI) {
CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
} else {
/* 5718 step 68 */
@@ -3378,7 +3378,7 @@
&sc->bge_pciecap, NULL) != 0)
|| (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)) {
/* PCIe */
- sc->bge_flags |= BGE_PCIE;
+ sc->bge_flags |= BGEF_PCIE;
/* Extract supported maximum payload size. */
reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,
sc->bge_pciecap + PCI_PCIE_DCAP);
@@ -3392,7 +3392,7 @@
} else if ((pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_PCISTATE) &
BGE_PCISTATE_PCI_BUSMODE) == 0) {
/* PCI-X */
- sc->bge_flags |= BGE_PCIX;
+ sc->bge_flags |= BGEF_PCIX;
if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX,
&sc->bge_pcixcap, NULL) == 0)
aprint_error_dev(sc->bge_dev,
@@ -3419,18 +3419,18 @@
case BGE_ASICREV_BCM5717:
case BGE_ASICREV_BCM5719:
case BGE_ASICREV_BCM5720:
- sc->bge_flags |= BGE_5717_PLUS;
+ sc->bge_flags |= BGEF_5717_PLUS;
/* FALLTHROUGH */
case BGE_ASICREV_BCM57765:
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