[src/trunk]: src/sys/arch/arm/arm Always supply all registers (don't make one...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/fecc0992ce6c
branches:  trunk
changeset: 782823:fecc0992ce6c
user:      matt <matt%NetBSD.org@localhost>
date:      Wed Nov 21 19:39:39 2012 +0000

description:
Always supply all registers (don't make one implicit).

diffstat:

 sys/arch/arm/arm/cpufunc_asm_armv7.S |  8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diffs (25 lines):

diff -r c74592f2fb46 -r fecc0992ce6c sys/arch/arm/arm/cpufunc_asm_armv7.S
--- a/sys/arch/arm/arm/cpufunc_asm_armv7.S      Wed Nov 21 19:38:36 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_armv7.S      Wed Nov 21 19:39:39 2012 +0000
@@ -48,8 +48,8 @@
        dsb                             @ data synchronization barrier
        mrc     p15, 0, r2, c0, c0, 5   @ get MPIDR
        cmp     r2, #0
-       orrlt   r0, #0x5b               @ MP, cachable (Normal WB)
-       orrge   r0, #0x1b               @ Non-MP, cacheable, normal WB
+       orrlt   r0, r0, #0x5b           @ MP, cachable (Normal WB)
+       orrge   r0, r0, #0x1b           @ Non-MP, cacheable, normal WB
        mcr     p15, 0, r0, c2, c0, 0   @ set the new TTB
 #ifdef MULTIPROCESSOR
        mcr     p15, 0, r0, c8, c3, 0   @ flush the I+D
@@ -76,8 +76,8 @@
 ENTRY_NP(armv7_setttb)
        mrc     p15, 0, r2, c0, c0, 5   @ get MPIDR
        cmp     r2, #0
-       orrlt   r0, #0x5b               @ MP, cachable (Normal WB)
-       orrge   r0, #0x1b               @ Non-MP, cacheable, normal WB
+       orrlt   r0, r0, #0x5b           @ MP, cachable (Normal WB)
+       orrge   r0, r0, #0x1b           @ Non-MP, cacheable, normal WB
        mcr     p15, 0, r0, c2, c0, 0   @ load new TTB
        cmp     r1, #0
 #ifdef MULTIPROCESSOR