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[src/netbsd-6]: src/sys/arch/x86/include Pull up the following revisisions, r...
details: https://anonhg.NetBSD.org/src/rev/a7f2197aef7b
branches: netbsd-6
changeset: 776855:a7f2197aef7b
user: martin <martin%NetBSD.org@localhost>
date: Mon Dec 29 15:31:06 2014 +0000
description:
Pull up the following revisisions, requested by msaitoh in #1220:
sys/arch/x86/include/specialreg.h 1.59-1.71, 1.73-1.81 (patch)
Update x86 special register definitions:
- Add latest CR4 bits.
- Recognize the P1GB and RDTSCP which were AMD-only on Intel HW too.
- Add some missing bit definitions for CPUID2 and those for XCR0.
- Fix CPUID_AMD_FLAGS4 to not try to print bits \41 and \42.
- Correct the comment about the extended family and model bits.
- Add some definitions related to the process extended state
enumeration.
- Add Intel Structured Extended Feature leaf (Fn0000_0007).
- Sort CPUID definitions in initial EAX value.
- Add Intel Deterministic Cache Parameter Leaf (CPUID leaf 4).
- Add some AMD Fn80000001 extended features %ecx bits definitions.
- "s/MXX/MMXX/" because this bit is "MMX eXtention".
- Add some definitions for cpu 'extended state' enumeration
(Fn0000000d).
- Add Energy Performance Bias bit of Fn0000_0006 %ecx.
- Add MSR_IA32_PLATFORM_ID (0x017)
- Modify comment.
- Style fix.
diffstat:
sys/arch/x86/include/specialreg.h | 395 +++++++++++++++++++++++++++----------
1 files changed, 285 insertions(+), 110 deletions(-)
diffs (truncated from 489 to 300 lines):
diff -r 5be40076bf46 -r a7f2197aef7b sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Mon Dec 29 15:14:26 2014 +0000
+++ b/sys/arch/x86/include/specialreg.h Mon Dec 29 15:31:06 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.55.2.3 2012/05/07 16:37:19 riz Exp $ */
+/* $NetBSD: specialreg.h,v 1.55.2.4 2014/12/29 15:31:06 martin Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -68,20 +68,55 @@
/* the remaining 7 bits of this register are reserved */
/*
- * bits in the pentiums %cr4 register:
+ * bits in the %cr4 control register:
*/
+#define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */
+#define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */
+#define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 */
+#define CR4_DE 0x00000008 /* debugging extension */
+#define CR4_PSE 0x00000010 /* large (4MB) page size enable */
+#define CR4_PAE 0x00000020 /* physical address extension enable */
+#define CR4_MCE 0x00000040 /* machine check enable */
+#define CR4_PGE 0x00000080 /* page global enable */
+#define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */
+#define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */
+#define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
+#define CR4_VMXE 0x00002000 /* enable VMX operations */
+#define CR4_SMXE 0x00004000 /* enable SMX operations */
+#define CR4_FSGSBASE 0x00010000 /* enable *FSBASE and *GSBASE instructions */
+#define CR4_PCIDE 0x00020000 /* enable Process Context IDentifiers */
+#define CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
+#define CR4_SMEP 0x00100000 /* enable SMEP support */
+#define CR4_SMAP 0x00200000 /* enable SMAP support */
-#define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */
-#define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */
-#define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */
-#define CR4_DE 0x00000008 /* debugging extension */
-#define CR4_PSE 0x00000010 /* large (4MB) page size enable */
-#define CR4_PAE 0x00000020 /* physical address extension enable */
-#define CR4_MCE 0x00000040 /* machine check enable */
-#define CR4_PGE 0x00000080 /* page global enable */
-#define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */
-#define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */
-#define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
+/*
+ * Extended Control Register XCR0
+ */
+#define XCR0_X87 0x00000001 /* x87 FPU/MMX state */
+#define XCR0_SSE 0x00000002 /* SSE state */
+#define XCR0_YMM_Hi128 0x00000004 /* AVX-256 (ymmn registers) */
+#define XCR0_BNDREGS 0x00000008 /* Memory protection ext bounds */
+#define XCR0_BNDCSR 0x00000010 /* Memory protection ext state */
+#define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */
+#define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */
+#define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */
+
+/*
+ * Known fpu bits - only these get enabled
+ * I think the XCR0_BNDREGS and XCR0_BNDCSR would need saving on
+ * every context switch.
+ * The save are is sized for all the fields below (max 2680 bytes).
+ */
+#define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \
+ XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM)
+
+#define XCR0_BND (XCR0_BNDREGS | XCR0_BNDCSR)
+
+#define XCR0_FLAGS1 "\20" \
+ "\1" "x87" "\2" "SSE" "\3" "AVX" \
+ "\4" "BNDREGS" "\5" "BNDCSR" \
+ "\6" "Opmask" "\7" "ZMM_Hi256" "\10" "Hi16_ZMM"
+
/*
* CPUID "features" bits
@@ -91,7 +126,7 @@
#define CPUID_FPU 0x00000001 /* processor has an FPU? */
#define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
#define CPUID_DE 0x00000004 /* has debugging extension */
-#define CPUID_PSE 0x00000008 /* has page 4MB page size extension */
+#define CPUID_PSE 0x00000008 /* has 4MB page size extension */
#define CPUID_TSC 0x00000010 /* has time stamp counter */
#define CPUID_MSR 0x00000020 /* has mode specific registers */
#define CPUID_PAE 0x00000040 /* has phys address extension */
@@ -121,11 +156,113 @@
#define CPUID_IA64 0x40000000 /* IA-64 architecture */
#define CPUID_SBF 0x80000000 /* signal break on FERR */
-#define CPUID_FLAGS1 "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE\10MCE\11CX8" \
- "\12APIC\13B10\14SEP\15MTRR\16PGE\17MCA\20CMOV" \
- "\21PAT\22PSE36\23PN\24CFLUSH\25B20\26DS\27ACPI" \
- "\30MMX\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM" \
- "\37IA64\40SBF"
+#define CPUID_FLAGS1 "\20" \
+ "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \
+ "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \
+ "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \
+ "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \
+ "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CFLUSH" \
+ "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \
+ "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \
+ "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF"
+
+/* Blacklists of CPUID flags - used to mask certain features */
+#ifdef XEN
+/* Not on Xen */
+#define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR)
+#else
+#define CPUID_FEAT_BLACKLIST 0
+#endif /* XEN */
+
+/*
+ * CPUID "features" bits in Fn00000001 %ecx
+ */
+
+#define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */
+#define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */
+#define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */
+#define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */
+#define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */
+#define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */
+#define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */
+#define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */
+#define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */
+#define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */
+#define CPUID2_CID 0x00000400 /* Context ID */
+/* bit 11 unused 0x00000800 */
+#define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */
+#define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */
+#define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */
+#define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */
+/* bit 16 unused 0x00010000 */
+#define CPUID2_PCID 0x00020000 /* Process Context ID */
+#define CPUID2_DCA 0x00040000 /* Direct Cache Access */
+#define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */
+#define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */
+#define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */
+#define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */
+#define CPUID2_POPCNT 0x00800000 /* popcount instruction available */
+#define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */
+#define CPUID2_AES 0x02000000 /* AES instructions */
+#define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */
+#define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */
+#define CPUID2_AVX 0x10000000 /* AVX instructions */
+#define CPUID2_F16C 0x20000000 /* half precision conversion */
+#define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */
+#define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */
+
+#define CPUID2_FLAGS1 "\20" \
+ "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \
+ "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \
+ "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "B11" \
+ "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \
+ "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \
+ "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \
+ "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \
+ "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ"
+
+#define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 0xf)
+#define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 0xf)
+#define CPUID2STEPPING(cpuid) ((cpuid) & 0xf)
+
+/*
+ * The Extended family bits should only be inspected when CPUID2FAMILY()
+ * returns 15. They are use to encode family value 16 to 270 (add 15).
+ * The Extended model hits are the high 4 bits of the model.
+ * They are only valid for family >= 15 or family 6 (intel, but all amd
+ * family 6 are documented to return zero bits for them).
+ */
+#define CPUID2EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff)
+#define CPUID2EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf)
+
+/*
+ * Intel Deterministic Cache Parameter Leaf
+ * Fn0000_0004
+ */
+
+/* %eax */
+#define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */
+#define CPUID_DCP_CACHETYPE_N 0 /* NULL */
+#define CPUID_DCP_CACHETYPE_D 1 /* Data cache */
+#define CPUID_DCP_CACHETYPE_I 2 /* Instruction cache */
+#define CPUID_DCP_CACHETYPE_U 3 /* Unified cache */
+#define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */
+#define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/
+#define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */
+#define CPUID_DCP_SHAREING __BITS(25, 14) /* shareing */
+#define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */
+
+/* %ebx */
+#define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */
+#define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */
+#define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */
+
+/* Number of sets: %ecx */
+
+/* %edx */
+#define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */
+#define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */
+#define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */
/*
* Intel Digital Thermal Sensor and
@@ -138,28 +275,104 @@
#define CPUID_DSPM_CME 0x00000020 /* Clock Modulation Extension */
#define CPUID_DSPM_PLTM 0x00000040 /* Package Level Thermal Management */
-#define CPUID_DSPM_FLAGS "\20\1DTS\2IDA\3ARAT\5PLN\6CME\7PLTM"
+#define CPUID_DSPM_FLAGS "\20" \
+ "\1" "DTS" "\2" "IDA" "\3" "ARAT" \
+ "\5" "PLN" "\6" "CME" "\7" "PLTM"
/*
* Intel Digital Thermal Sensor and
* Power Management, Fn0000_0006 - %ecx.
*/
#define CPUID_DSPM_HWF 0x00000001 /* MSR_APERF/MSR_MPERF available */
+#define CPUID_DSPM_EPB 0x00000008 /* Energy Performance Bias */
-#define CPUID_DSPM_FLAGS1 "\20\1HWF"
+#define CPUID_DSPM_FLAGS1 "\20" "\1" "HWF" "\4" "EPB"
+
+/*
+ * Intel Structured Extended Feature leaf
+ * Fn0000_0007 main leaf - %ebx.
+ */
+#define CPUID_SEF_FSGSBASE __BIT(0)
+#define CPUID_SEF_TSC_ADJUST __BIT(1)
+#define CPUID_SEF_BMI1 __BIT(3)
+#define CPUID_SEF_HLE __BIT(4)
+#define CPUID_SEF_AVX2 __BIT(5)
+#define CPUID_SEF_SMEP __BIT(7)
+#define CPUID_SEF_BMI2 __BIT(8)
+#define CPUID_SEF_ERMS __BIT(9)
+#define CPUID_SEF_INVPCID __BIT(10)
+#define CPUID_SEF_RTM __BIT(11)
+#define CPUID_SEF_QM __BIT(12)
+#define CPUID_SEF_FPUCSDS __BIT(13)
+#define CPUID_SEF_MPX __BIT(14)
+#define CPUID_SEF_PQE __BIT(15)
+#define CPUID_SEF_AVX512F __BIT(16)
+#define CPUID_SEF_RDSEED __BIT(18)
+#define CPUID_SEF_ADX __BIT(19)
+#define CPUID_SEF_SMAP __BIT(20)
+#define CPUID_SEF_PT __BIT(25)
+#define CPUID_SEF_AVX512PF __BIT(26)
+#define CPUID_SEF_AVX512ER __BIT(27)
+#define CPUID_SEF_AVX512CD __BIT(28)
+#define CPUID_SEF_SHA __BIT(29)
+
+#define CPUID_SEF_FLAGS "\20" \
+ "\1" "FSGSBASE" "\2" "TSCADJUST" "\4" "BMI1" \
+ "\5" "HLE" "\6" "AVX2" "\10" "SMEP" \
+ "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \
+ "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \
+ "\21" "AVX512F" "\23" "RDSEED" "\24" "ADX" \
+ "\25" "SMAP" \
+ "\32" "PT" "\33" "AVX512PF""\34" "AVX512ER"\
+ "\35" "AVX512CD""\36" "SHA"
+
+/*
+ * CPUID Processor extended state Enumeration Fn0000000d
+ *
+ * %ecx == 0: supported features info:
+ * %eax: Valid bits of lower 32bits of XCR0
+ * %ebx Save area size for features enabled in XCR0
+ * %ecx Maximim save area size for all cpu features
+ * %edx: Valid bits of upper 32bits of XCR0
+ *
+ * %ecx == 1:
+ * %eax: Bit 0 => xsaveopt instruction avalaible (sandy bridge onwards)
+ *
+ * %ecx >= 2: Save area details for XCR0 bit n
+ * %eax: size of save area for this feature
+ * %ebx: offset of save area for this feature
+ * %ecx, %edx: reserved
+ * All of %eax, %ebx, %ecx and %edx are zero for unsupported features.
+ */
+
+#define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */
+#define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */
+#define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */
+#define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */
+
+#define CPUID_PES1_FLAGS "\20" \
+ "\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES"
/* Intel Fn80000001 extended features - %edx */
#define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */
#define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */
+#define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */
+#define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */
#define CPUID_EM64T 0x20000000 /* Intel EM64T */
-#define CPUID_INTEL_EXT_FLAGS "\20\14SYSCALL/SYSRET\25XD\36EM64T"
+#define CPUID_INTEL_EXT_FLAGS "\20" \
+ "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \
+ "\34" "RDTSCP" "\36" "EM64T"
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