[src/trunk]: src/sys/arch/hppa/hppa Correct/add comments.

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e6ddfe948678
branches:  trunk
changeset: 749909:e6ddfe948678
user:      skrll <skrll%NetBSD.org@localhost>
date:      Sat Dec 12 15:25:32 2009 +0000

description:
Correct/add comments.

diffstat:

 sys/arch/hppa/hppa/trap.S |  199 ++++++++++++++++++++++++++++-----------------
 1 files changed, 124 insertions(+), 75 deletions(-)

diffs (truncated from 318 to 300 lines):

diff -r 09a471360d84 -r e6ddfe948678 sys/arch/hppa/hppa/trap.S
--- a/sys/arch/hppa/hppa/trap.S Sat Dec 12 15:10:34 2009 +0000
+++ b/sys/arch/hppa/hppa/trap.S Sat Dec 12 15:25:32 2009 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: trap.S,v 1.32 2009/12/10 05:10:01 rmind Exp $  */
+/*     $NetBSD: trap.S,v 1.33 2009/12/12 15:25:32 skrll Exp $  */
 
 /*-
  * Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -1302,14 +1302,15 @@
        extru   %r17, 24, 25, %r17
 
        .align  32
+
 /*
- * This is a handler for interruption 20, "TLB dirty bit trap".  It
- * is used on the PA7000 (PCX), PA7000 (PCX-S), and PA7100 (PCX-T). XXXNH
+ * This is a handler for interruption 20, "TLB dirty bit trap".  It is used on
+ * the PA7000 (PCX), PA7000 (PCX-S), and PA7100 (PCX-T).
  * Only shadowed registers are available, and they are:
  *
  * %r1 = C trap number
- * %r8 = data address space identifier
- * %r9 = data address offset
+ * %r8 = data address space identifier. Copied from %isr
+ * %r9 = data address offset. Copied from %ior
  * %r16 = undefined
  * %r17 = undefined
  * %r24 = undefined
@@ -1331,15 +1332,13 @@
 EXIT(TLABEL(tlbd_s))
 
 /*
- * This is a handler for interruption 6, "Instruction TLB miss fault",
- * and interruption 16, "Non-access instruction TLB miss fault".  It
- * is used on the PA7000 (PCX), PA7000 (PCX-S), PA7100 (PCX-T) and
- * PA7200 (PCX-T')
+ * This is a handler for interruption 6, "Instruction TLB miss fault". It is
+ * used on the PA7000 (PCX), PA7000 (PCX-S), PA7100 (PCX-T) and PA7200 (PCX-T')
  * Only shadowed registers are available, and they are:
  *
  * %r1 = C trap number
- * %r8 = instruction address space identifier
- * %r9 = instruction address offset
+ * %r8 = instruction address space identifier. Copied from %pcsq
+ * %r9 = instruction address offset. Copied from %pcoq
  * %r16 = undefined
  * %r17 = undefined
  * %r24 = undefined
@@ -1363,15 +1362,13 @@
 EXIT(TLABEL(itlb_s))
 
 /*
- * This is a handler for interruption 15, "Data TLB miss fault",
- * and interruption 17, "Non-access data TLB miss fault".  It is
- * used on the PA7000 (PCX), PA7000 (PCX-S), PA7100 (PCX-T) and
- * PA7200 (PCX-T')
+ * This is a handler for interruption 15, "Data TLB miss fault".  It is used on
+ * the PA7000 (PCX), PA7000 (PCX-S), PA7100 (PCX-T) and PA7200 (PCX-T').
  * Only shadowed registers are available, and they are:
  *
  * %r1 = C trap number
- * %r8 = data address space identifier
- * %r9 = data address offset
+ * %r8 = data address space identifier.  Copied from %isr.
+ * %r9 = data address offset.  Copied from %ior.
  * %r16 = undefined
  * %r17 = undefined
  * %r24 = undefined
@@ -1392,6 +1389,22 @@
        nop
 EXIT(TLABEL(dtlb_s))
 
+/*
+ * This is a handler for interruption 16, "Non-access instruction TLB miss
+ * fault", and interrupt 17, "Non-access data TLB miss fault / Non-access data
+ * page fault".  It is used on the PA7000 (PCX), PA7000 (PCX-S), PA7100 (PCX-T)
+ * and PA7200 (PCX-T').
+ *
+ * Only shadowed registers are available, and they are:
+ *
+ * %r1 = C trap number
+ * %r8 = instruction address space identifier. Copied from %isr.
+ * %r9 = instruction address offset. Copied from %ior.
+ * %r16 = undefined
+ * %r17 = undefined
+ * %r24 = undefined
+ * %r25 = undefined
+ */
 LEAF_ENTRY_NOPROFILE(TLABEL(dtlbna_s))
 ALTENTRY(TLABEL(itlbna_s))
 ALTENTRY(TLABEL(dtlbna_t))
@@ -1470,36 +1483,22 @@
        extru   %r17, 24, 25, %r17      /* tlbbtop(%r17) */             ! \
        sync
 
+       .align  32
+
 /*
- * This is a handler for interruption 20, "TLB dirty bit trap".  It
- * is used on the PA7100LC (PCX-L), PA7300LC (PCX-L2), PA8000 (PCX-U),
- * PA8200 (PCX-W), PA8500 (PCX-W), and PA8600 (PCX-W+).  Only shadowed 
- * registers are available, and they are:
+ * This is a handler for interruption 20, "TLB dirty bit trap".  It is used on
+ * the PA7100LC (PCX-L), PA7300LC (PCX-L2).
+ * Only shadowed registers are available, and they are:
  *
  * %r1 = C trap number
- * %r8 = data address space identifier
- * %r9 = data address offset
+ * %r8 = data address space identifier.  Copied from %ior.
+ * %r9 = data address offset  Copied from %isr.
  * %r16 = undefined
  * %r17 = undefined
  * %r24 = undefined
  * %r25 = undefined
  */
 
-/*
- * This is a handler for interruption 20, "TLB dirty bit trap".  It
- * is used on the PA7100LC (PCX-L), PA7300LC (PCX-L2). Only shadowed
- * registers are available, and they are:
- *
- * %r1 = C trap number
- * %r8 = data address space identifier
- * %r9 = data address offset
- * %r16 = undefined
- * %r17 = undefined
- * %r24 = undefined
- * %r25 = undefined
- */
-
-       .align  32
 LEAF_ENTRY_NOPROFILE(TLABEL(tlbd_l))
        TLB_STATS_PRE(tlbd)
        TLB_PULL_L(1, TLABEL(all))
@@ -1519,14 +1518,13 @@
 EXIT(TLABEL(tlbd_l))
 
 /*
- * This is a handler for interruption 6, "Instruction TLB miss fault",
- * and interruption 16, "Non-access instruction TLB miss fault".  It
- * is used on the PA7100LC (PCX-L), PA7300LC (PCX-L2).  Only shadowed
- * registers are available, and they are:
+ * This is a handler for interruption 6, "Instruction TLB miss fault".  It is
+ * used on the PA7100LC (PCX-L), PA7300LC (PCX-L2).
+ * Only shadowed registers are available, and they are:
  *
  * %r1 = C trap number
- * %r8 = instruction address space identifier
- * %r9 = instruction address offset
+ * %r8 = instruction address space identifier. Copied from %pcsq.
+ * %r9 = instruction address offset. Copied from %pcoq.
  * %r16 = undefined
  * %r17 = undefined
  * %r24 = undefined
@@ -1550,6 +1548,20 @@
        nop
 EXIT(TLABEL(itlb_l))
 
+/*
+ * This is a handler for interruption 16, "Non-access instruction TLB miss
+ * fault", and interrupt 17, "Non-access data TLB miss fault / Non-access data
+ * page fault".  It is used on the PA7100LC (PCX-L), PA7300LC (PCX-L2).
+ * Only shadowed registers are available, and they are:
+ *
+ * %r1 = C trap number
+ * %r8 = instruction address space identifier. Copied from %isr.
+ * %r9 = instruction address offset. Copied from %ior.
+ * %r16 = undefined
+ * %r17 = undefined
+ * %r24 = undefined
+ * %r25 = undefined
+ */
 LEAF_ENTRY_NOPROFILE(TLABEL(dtlbna_l))
 ALTENTRY(TLABEL(itlbna_l))
        TLB_STATS_PRE(dtlb)
@@ -1579,6 +1591,19 @@
        nop
 EXIT(TLABEL(dtlbna_l))
 
+/*
+ * This is a handler for interruption 15, "Data TLB miss fault".  It is used on
+ * the PA7100LC (PCX-L), PA7300LC (PCX-L2).
+ * Only shadowed registers are available, and they are:
+ *
+ * %r1 = C trap number
+ * %r8 = instruction address space identifier. Copied from %isr.
+ * %r9 = instruction address offset. Copied from %ior.
+ * %r16 = undefined
+ * %r17 = undefined
+ * %r24 = undefined
+ * %r25 = undefined
+ */
 LEAF_ENTRY_NOPROFILE(TLABEL(dtlb_l))
        TLB_STATS_PRE(dtlb)
        TLB_PULL_L(0, TLABEL(all))
@@ -1651,6 +1676,19 @@
        depdi   0, 44, 30, %r25                 ! \
        depd    %r16, 14, 15, %r25
 
+/*
+ * This is a handler for interruption 20, "TLB dirty bit trap".  It is used by
+ * the PA8000 (PCX-U), PA8200 (PCX-W), PA8500 (PCX-W), and PA8600 (PCX-W+).
+ * Only shadowed registers are available, and they are:
+ *
+ * %r1 = C trap number
+ * %r8 = data address space identifier.  Copied from %isr.
+ * %r9 = data address offset.  Copied from %ior.
+ * %r16 = undefined
+ * %r17 = undefined
+ * %r24 = undefined
+ * %r25 = undefined
+ */
 LEAF_ENTRY_NOPROFILE(TLABEL(tlbd_u))
        TLB_STATS_PRE(tlbd)
        TLB_PULL_L(1, TLABEL(all))
@@ -1661,6 +1699,19 @@
        nop
 EXIT(TLABEL(tlbd_u))
 
+/*
+ * This is a handler for interruption 6, "Instruction TLB miss fault".  It is
+ * the PA8000 (PCX-U), PA8200 (PCX-W), PA8500 (PCX-W), and PA8600 (PCX-W+).
+ * Only shadowed registers are available, and they are:
+ *
+ * %r1 = C trap number
+ * %r8 = data address space identifier.   Copied from %isr.
+ * %r9 = data address offset.  Copied from %ior.
+ * %r16 = undefined
+ * %r17 = undefined
+ * %r24 = undefined
+ * %r25 = undefined
+ */
 LEAF_ENTRY_NOPROFILE(TLABEL(itlb_u))
        TLB_STATS_PRE(itlb)
        TLB_PULL_L(0, TLABEL(all))
@@ -1673,6 +1724,22 @@
        nop
 EXIT(TLABEL(itlb_u))
 
+
+/*
+ * This is a handler for interruption 16, "Non-access instruction TLB miss
+ * fault", and interrupt 17, "Non-access data TLB miss fault / Non-access data
+ * page fault".  It is the PA8000 (PCX-U), PA8200 (PCX-W), PA8500 (PCX-W),
+ * and PA8600 (PCX-W+).
+ * Only shadowed registers are available, and they are:
+ *
+ * %r1 = C trap number
+ * %r8 = instruction address space identifier. Copied from %isr.
+ * %r9 = instruction address offset. Copied from %ior.
+ * %r16 = undefined
+ * %r17 = undefined
+ * %r24 = undefined
+ * %r25 = undefined
+ */
 LEAF_ENTRY_NOPROFILE(TLABEL(dtlbna_u))
 ALTENTRY(TLABEL(itlbna_u))
        TLB_STATS_PRE(dtlb)
@@ -1701,6 +1768,19 @@
        nop
 EXIT(TLABEL(dtlbna_u))
 
+/*
+ * This is a handler for interruption 15, "Data TLB miss fault".  It is the
+ * PA8000 (PCX-U), PA8200 (PCX-W), PA8500 (PCX-W), and PA8600 (PCX-W+).
+ * Only shadowed registers are available, and they are:
+ *
+ * %r1 = C trap number
+ * %r8 = instruction address space identifier. Copied from %isr.
+ * %r9 = instruction address offset. Copied from %ior.
+ * %r16 = undefined
+ * %r17 = undefined
+ * %r24 = undefined
+ * %r25 = undefined
+ */
 LEAF_ENTRY_NOPROFILE(TLABEL(dtlb_u))
        TLB_STATS_PRE(dtlb)
        TLB_PULL_L(0, TLABEL(all))
@@ -1847,37 +1927,6 @@
 
 #endif /* defined(HP7100LC_CPU) || defined(HP7300LC_CPU) */
 
-/*
- * This is a handler for interruption 17, "Non-access data TLB miss 
- * fault".  It is used on the PA7100LC (PCX-L), PA7300LC (PCX-L2), 
- * PA8000 (PCX-U), PA8200 (PCX-W), PA8500 (PCX-W), and PA8600 (PCX-W+).
- * Only shadowed registers are available, and they are:
- *
- * %r1 = C trap number
- * %r8 = data address space identifier
- * %r9 = data address offset
- * %r16 = undefined
- * %r17 = undefined
- * %r24 = undefined
- * %r25 = undefined
- */
-
-