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[src/trunk]: src/sys/arch Make GDIUM build again after matt-nb5-mips64 merge....
details: https://anonhg.NetBSD.org/src/rev/d8af52cb8850
branches: trunk
changeset: 765877:d8af52cb8850
user: bouyer <bouyer%NetBSD.org@localhost>
date: Wed Jun 08 17:47:48 2011 +0000
description:
Make GDIUM build again after matt-nb5-mips64 merge. untested as I don't have
this hardware, but I'll use this as a base for Lemote Fulong support.
diffstat:
sys/arch/evbmips/conf/files.gdium | 3 +-
sys/arch/evbmips/gdium/gdium_dma.c | 25 ++++----------
sys/arch/evbmips/gdium/gdium_intr.c | 64 ++++++++++++------------------------
sys/arch/evbmips/gdium/machdep.c | 59 +++++++--------------------------
sys/arch/mips/mips/cache.c | 50 ++++++++++++++--------------
sys/arch/mips/mips/cache_ls2.c | 37 ++++++++++++--------
6 files changed, 89 insertions(+), 149 deletions(-)
diffs (truncated from 585 to 300 lines):
diff -r 2e2125cf1eb7 -r d8af52cb8850 sys/arch/evbmips/conf/files.gdium
--- a/sys/arch/evbmips/conf/files.gdium Wed Jun 08 17:19:20 2011 +0000
+++ b/sys/arch/evbmips/conf/files.gdium Wed Jun 08 17:47:48 2011 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.gdium,v 1.1 2009/08/06 00:50:25 matt Exp $
+# $NetBSD: files.gdium,v 1.2 2011/06/08 17:47:48 bouyer Exp $
file arch/evbmips/gdium/gdium_bus_io.c
file arch/evbmips/gdium/gdium_bus_mem.c
@@ -15,7 +15,6 @@
file arch/mips/mips/mips3_clock.c
file arch/mips/mips/mips3_clockintr.c
-file arch/mips/mips/softintr.c
# The autoconfiguration root.
device mainbus { [addr = -1] }
diff -r 2e2125cf1eb7 -r d8af52cb8850 sys/arch/evbmips/gdium/gdium_dma.c
--- a/sys/arch/evbmips/gdium/gdium_dma.c Wed Jun 08 17:19:20 2011 +0000
+++ b/sys/arch/evbmips/gdium/gdium_dma.c Wed Jun 08 17:47:48 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gdium_dma.c,v 1.2 2009/08/06 16:37:01 matt Exp $ */
+/* $NetBSD: gdium_dma.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gdium_dma.c,v 1.2 2009/08/06 16:37:01 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gdium_dma.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $");
#include <sys/param.h>
@@ -55,20 +55,9 @@
t = &gc->gc_pci_dmat;
t->_cookie = gc;
t->_wbase = GDIUM_DMA_PCI_PCIBASE;
- t->_physbase = GDIUM_DMA_PCI_PHYSBASE;
- t->_wsize = GDIUM_DMA_PCI_SIZE;
- t->_dmamap_create = _bus_dmamap_create;
- t->_dmamap_destroy = _bus_dmamap_destroy;
- t->_dmamap_load = _bus_dmamap_load;
- t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
- t->_dmamap_load_uio = _bus_dmamap_load_uio;
- t->_dmamap_load_raw = _bus_dmamap_load_raw;
- t->_dmamap_unload = _bus_dmamap_unload;
- t->_dmamap_sync = _bus_dmamap_sync;
-
- t->_dmamem_alloc = _bus_dmamem_alloc;
- t->_dmamem_free = _bus_dmamem_free;
- t->_dmamem_map = _bus_dmamem_map;
- t->_dmamem_unmap = _bus_dmamem_unmap;
- t->_dmamem_mmap = _bus_dmamem_mmap;
+ t->_bounce_alloc_lo = GDIUM_DMA_PCI_PHYSBASE;
+ t->_bounce_alloc_hi = GDIUM_DMA_PCI_PHYSBASE + GDIUM_DMA_PCI_SIZE;
+ t->_dmamap_ops = mips_bus_dmamap_ops;
+ t->_dmamem_ops = mips_bus_dmamem_ops;
+ t->_dmatag_ops = mips_bus_dmatag_ops;
}
diff -r 2e2125cf1eb7 -r d8af52cb8850 sys/arch/evbmips/gdium/gdium_intr.c
--- a/sys/arch/evbmips/gdium/gdium_intr.c Wed Jun 08 17:19:20 2011 +0000
+++ b/sys/arch/evbmips/gdium/gdium_intr.c Wed Jun 08 17:47:48 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gdium_intr.c,v 1.2 2009/08/07 01:27:14 matt Exp $ */
+/* $NetBSD: gdium_intr.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -37,7 +37,10 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gdium_intr.c,v 1.2 2009/08/07 01:27:14 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gdium_intr.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $");
+
+#define __INTR_PRIVATE
+
#include "opt_ddb.h"
@@ -129,7 +132,7 @@
};
struct gdium_cpuintr gdium_cpuintrs[NINTRS];
-const char *gdium_cpuintrnames[NINTRS] = {
+const char * const gdium_cpuintrnames[NINTRS] = {
"int 0 (pci)",
"int 1 (errors)",
};
@@ -138,20 +141,11 @@
* This is a mask of bits to clear in the SR when we go to a
* given hardware interrupt priority level.
*/
-const uint32_t ipl_sr_bits[_IPL_N] = {
- [IPL_NONE] = 0,
- [IPL_SOFTCLOCK] =
- MIPS_SOFT_INT_MASK_0,
-#if IPL_SOFTCLOCK != IPL_SOFTBIO
- [IPL_SOFTBIO] =
- MIPS_SOFT_INT_MASK_0,
-#endif
- [IPL_SOFTNET] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
-#if IPL_SOFTNET != IPL_SOFTSERIAL
- [IPL_SOFTSERIAL] =
- MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
-#endif
+static const struct ipl_sr_map gdium_ipl_sr_map = {
+ .sr_bits = {
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
[IPL_VM] =
MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
MIPS_INT_MASK_0 |
@@ -167,25 +161,12 @@
MIPS_INT_MASK_3 |
MIPS_INT_MASK_4 |
MIPS_INT_MASK_5,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
};
-/*
- * This is a mask of bits to clear in the SR when we go to a
- * given software interrupt priority level.
- * Hardware ipls are port/board specific.
- */
-const uint32_t mips_ipl_si_to_sr[] = {
- [IPL_SOFTCLOCK-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
-#if IPL_SOFTCLOCK != IPL_SOFTBIO
- [IPL_SOFTBIO-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
-#endif
- [IPL_SOFTNET-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_1,
-#if IPL_SOFTNET != IPL_SOFTSERIAL
- [IPL_SOFTSERIAL-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_1,
-#endif
-};
-
-int gdium_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
+int gdium_pci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
const char *gdium_pci_intr_string(void *, pci_intr_handle_t);
const struct evcnt *gdium_pci_intr_evcnt(void *, pci_intr_handle_t);
void *gdium_pci_intr_establish(void *, pci_intr_handle_t, int,
@@ -196,11 +177,13 @@
void
evbmips_intr_init(void)
{
- struct gdium_config *gc = &gdium_configuration;
+ struct gdium_config * const gc = &gdium_configuration;
struct bonito_config *bc = &gc->gc_bonito;
const struct gdium_irqmap *irqmap;
uint32_t intbit;
- int i;
+ size_t i;
+
+ ipl_sr_map = gdium_ipl_sr_map;
for (i = 0; i < NINTRS; i++) {
LIST_INIT(&gdium_cpuintrs[i].cintr_list);
@@ -316,8 +299,7 @@
}
void
-evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc,
- uint32_t ipending)
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
{
const struct gdium_irqmap *irqmap;
struct evbmips_intrhand *ih;
@@ -341,11 +323,7 @@
(*ih->ih_func)(ih->ih_arg);
}
}
- cause &= ~(MIPS_INT_MASK_0 << level);
}
-
- /* Re-enable anything that we have processed. */
- _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
}
/*****************************************************************************
@@ -353,7 +331,7 @@
*****************************************************************************/
int
-gdium_pci_intr_map(struct pci_attach_args *pa,
+gdium_pci_intr_map(const struct pci_attach_args *pa,
pci_intr_handle_t *ihp)
{
static const int8_t pciirqmap[5/*device*/] = {
diff -r 2e2125cf1eb7 -r d8af52cb8850 sys/arch/evbmips/gdium/machdep.c
--- a/sys/arch/evbmips/gdium/machdep.c Wed Jun 08 17:19:20 2011 +0000
+++ b/sys/arch/evbmips/gdium/machdep.c Wed Jun 08 17:47:48 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.13 2011/02/20 07:48:34 matt Exp $ */
+/* $NetBSD: machdep.c,v 1.14 2011/06/08 17:47:48 bouyer Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -74,7 +74,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.13 2011/02/20 07:48:34 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.14 2011/06/08 17:47:48 bouyer Exp $");
#include "opt_ddb.h"
#include "opt_execfmt.h"
@@ -106,6 +106,8 @@
#include <machine/cpu.h>
#include <machine/psl.h>
+#include <mips/locore.h>
+
#include <mips/bonito/bonitoreg.h>
#include <evbmips/gdium/gdiumvar.h>
@@ -126,9 +128,6 @@
/* For sysctl_hw. */
extern char cpu_model[];
-/* Our exported CPU info; we can have only one. */
-struct cpu_info cpu_info_store;
-
/* Maps for VM objects. */
struct vm_map *phys_map = NULL;
@@ -200,9 +199,6 @@
{
struct gdium_config *gc = &gdium_configuration;
void *kernend;
- u_long first, last;
- struct pcb *pcb0;
- vaddr_t v;
#ifdef NOTYET
char *cp;
int howto;
@@ -225,7 +221,7 @@
* first printf() after that is called).
* Also clears the I+D caches.
*/
- mips_vector_init(NULL, bool);
+ mips_vector_init(NULL, false);
/* set the VM page size */
uvm_setpagesize();
@@ -261,7 +257,7 @@
}
}
- if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
+ if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
curcpu()->ci_cpu_freq /= 2;
/* Compute the number of ticks for hz. */
@@ -275,7 +271,7 @@
* Get correct cpu frequency if the CPU runs at twice the
* external/cp0-count frequency.
*/
- if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
+ if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
curcpu()->ci_cpu_freq *= 2;
#ifdef DEBUG
@@ -330,10 +326,8 @@
/*
* Load the rest of the available pages into the VM system.
*/
- first = round_page(MIPS_KSEG0_TO_PHYS(kernend));
- last = mem_clusters[0].start + mem_clusters[0].size;
- uvm_page_physload(atop(first), atop(last), atop(first), atop(last),
- VM_FREELIST_DEFAULT);
+ mips_page_physload(MIPS_KSEG0_START, (vaddr_t)kernend,
+ mem_clusters, mem_cluster_cnt, NULL, 0);
/*
* Initialize error message buffer (at end of core).
@@ -345,13 +339,7 @@
/*
* Allocate uarea page for lwp0 and set it.
*/
- v = uvm_pageboot_alloc(USPACE);
- uvm_lwp_setuarea(&lwp0, v);
-
- pcb0 = lwp_getpcb(&lwp0);
- pcb0->pcb_context[11] = MIPS_INT_MASK | MIPS_SR_INT_IE; /* SR */
-
- lwp0.l_md.md_regs = (struct frame *)(v + USPACE) - 1;
+ mips_init_lwp0_uarea();
/*
* Initialize debuggers, and break into them, if appropriate.
@@ -378,15 +366,10 @@
void
cpu_startup(void)
{
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