[src/trunk]: src/sys/dev/pci Define and use symbolic bits in registers.

[jakllsch <jakllsch%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/ea186f6895a9
branches:  trunk
changeset: 769908:ea186f6895a9
user:      jakllsch <jakllsch%NetBSD.org@localhost>
date:      Mon Sep 26 18:07:37 2011 +0000

description:
Define and use symbolic bits in registers.

diffstat:

 sys/dev/pci/cxdtv.c    |  23 +++++++++++------------
 sys/dev/pci/cxdtvreg.h |  33 ++++++++++++++++++++++++++++-----
 2 files changed, 39 insertions(+), 17 deletions(-)

diffs (136 lines):

diff -r 9db78bfb9508 -r ea186f6895a9 sys/dev/pci/cxdtv.c
--- a/sys/dev/pci/cxdtv.c       Mon Sep 26 15:19:45 2011 +0000
+++ b/sys/dev/pci/cxdtv.c       Mon Sep 26 18:07:37 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cxdtv.c,v 1.8 2011/08/29 14:47:08 jmcneill Exp $ */
+/* $NetBSD: cxdtv.c,v 1.9 2011/09/26 18:07:37 jakllsch Exp $ */
 
 /*
  * Copyright (c) 2008, 2011 Jonathan A. Kollasch
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cxdtv.c,v 1.8 2011/08/29 14:47:08 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cxdtv.c,v 1.9 2011/09/26 18:07:37 jakllsch Exp $");
 
 #include <sys/param.h>
 #include <sys/kernel.h>
@@ -780,7 +780,7 @@
 
        rm = sc->sc_riscbuf;
 
-       /* htole32 will be done when program is copied to chip sram */
+       /* htole32 will be done when program is copied to chip SRAM */
 
        /* XXX */
        *(rm++) = (CX_RISC_SYNC|0);
@@ -881,33 +881,32 @@
 
        /* software reset */
 
-       /* serial MPEG port on HD5500 */
        switch(sc->sc_vendor) {
        case PCI_VENDOR_ATI:
                /* both ATI boards with DTV are the same */
                bus_space_write_4(sc->sc_memt, sc->sc_memh,
-                   CXDTV_TS_GEN_CONTROL, 0x40);
+                   CXDTV_TS_GEN_CONTROL, IPB_SW_RST);
                delay(100);
                /* parallel MPEG port */
                bus_space_write_4(sc->sc_memt, sc->sc_memh,
-                   CXDTV_PINMUX_IO, 0x80); /* XXX bit defines */
+                   CXDTV_PINMUX_IO, MPEG_PAR_EN);
                break;
        case PCI_VENDOR_PCHDTV:
                if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) {
                        bus_space_write_4(sc->sc_memt, sc->sc_memh,
-                           CXDTV_TS_GEN_CONTROL, 0x48);
+                           CXDTV_TS_GEN_CONTROL, IPB_SW_RST|IPB_SMODE);
                        delay(100);
-                       /* serial MPEG port */
                        bus_space_write_4(sc->sc_memt, sc->sc_memh,
-                           CXDTV_PINMUX_IO, 0x00); /* XXX bit defines */
+                           CXDTV_PINMUX_IO, 0x00); /* serial MPEG port */
                        /* byte-width start-of-packet */
                        bus_space_write_4(sc->sc_memt, sc->sc_memh,
                            CXDTV_HW_SOP_CONTROL,
                            0x47 << 16 | 188 << 4 | 1);
                        bus_space_write_4(sc->sc_memt, sc->sc_memh,
-                           CXDTV_TS_SOP_STATUS, 1 << 13);
+                           CXDTV_TS_SOP_STATUS, IPB_SOP_BYTEWIDE);
+                       /* serial MPEG port on HD5500 */
                        bus_space_write_4(sc->sc_memt, sc->sc_memh,
-                           CXDTV_TS_GEN_CONTROL, 0x08);
+                           CXDTV_TS_GEN_CONTROL, IPB_SMODE);
                }
                break;
        default:
@@ -917,7 +916,7 @@
        bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_LNGTH,
            CXDTV_TS_PKTSIZE);
 
-       /* Configure for standard MPEG TS, 1 good to sync  */
+       /* Configure for standard MPEG TS, 1 good packet to sync  */
        bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_HW_SOP_CONTROL,
            0x47 << 16 | 188 << 4 | 1);
 
diff -r 9db78bfb9508 -r ea186f6895a9 sys/dev/pci/cxdtvreg.h
--- a/sys/dev/pci/cxdtvreg.h    Mon Sep 26 15:19:45 2011 +0000
+++ b/sys/dev/pci/cxdtvreg.h    Mon Sep 26 18:07:37 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cxdtvreg.h,v 1.1 2011/07/11 00:46:04 jakllsch Exp $ */
+/* $NetBSD: cxdtvreg.h,v 1.2 2011/09/26 18:07:38 jakllsch Exp $ */
 
 /*-
  * Copyright (c) 2007 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -76,7 +76,10 @@
 
 #define CXDTV_DEV_CNTRL2_RUN_RISC __BIT(5)
 
-/* mpeg ts registers */
+/* PINMUX_IO */
+#define MPEG_PAR_EN            __BIT(7)
+
+/* MPEG TS registers */
 
 #define CXDTV_DMA28_PTR1       0x30009c
 #define CXDTV_DMA28_PTR2       0x3000dc
@@ -98,14 +101,34 @@
 #define CXDTV_TS_INT_MSTAT     0x200078
 #define CXDTV_TS_INT_SSTAT     0x20007c
 
-/* for TS_DMA_CNTRL */
+/* TS_DMA_CNTRL */
 #define CXDTV_TS_RISC_EN       __BIT(4)
 #define CXDTV_TS_FIFO_EN       __BIT(0)
 
-#define CXDTV_TS_RISCI2                0x10
-#define CXDTV_TS_RISCI1                0x01
+/* TS_INT_* */
+#define CXDTV_TS_RISCI2                __BIT(4)
+#define CXDTV_TS_RISCI1                __BIT(0)
 #define CXDTV_TS_RISCI         (CXDTV_TS_RISCI2|CXDTV_TS_RISCI1)
 
+/* HW_SOP_CONTROL */
+
+/* TS_GEN_CONTROL */
+#define MPEG_IN_SYNC           __BIT(0)
+#define IPB_MCLK_POL           __BIT(1)
+#define IPB_PUNC_CLK           __BIT(2)
+#define IPB_SMODE              __BIT(3)
+#define IPB_BIT_RVRS           __BIT(4)
+#define IPB_ERR_ACK            __BIT(5)
+#define IPB_SW_RST             __BIT(6)
+#define IPB_STAT_CLR           __BIT(7)
+
+/* TS_SOP_STATUS */
+#define MPG_BAD_SOP_STAT       __BITS(11,0)
+#define IPB_SOP_SYNC_CHK       __BIT(12)
+#define IPB_SOP_BYTEWIDE       __BIT(13)
+#define IPB_SOP_SEL            __BITS(15, 14)
+#define IPB_TSSOP_POL          __BIT(16)
+
 /* RISC instructions */
 #define CX_RISC_WRITECR                0xd0000000
 #define CX_RISC_WRITECM                0xc0000000