[src/trunk]: src/sys/arch/arm/footbridge Whitespace.

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/55e431c80e2c
branches:  trunk
changeset: 758865:55e431c80e2c
user:      skrll <skrll%NetBSD.org@localhost>
date:      Thu Nov 18 18:06:21 2010 +0000

description:
Whitespace.

diffstat:

 sys/arch/arm/footbridge/footbridge_io.c |  25 ++++++++++++-------------
 1 files changed, 12 insertions(+), 13 deletions(-)

diffs (46 lines):

diff -r ae3b5f2610d7 -r 55e431c80e2c sys/arch/arm/footbridge/footbridge_io.c
--- a/sys/arch/arm/footbridge/footbridge_io.c   Thu Nov 18 18:01:20 2010 +0000
+++ b/sys/arch/arm/footbridge/footbridge_io.c   Thu Nov 18 18:06:21 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: footbridge_io.c,v 1.16 2009/12/15 21:38:20 skrll Exp $ */
+/*     $NetBSD: footbridge_io.c,v 1.17 2010/11/18 18:06:21 skrll Exp $ */
 
 /*
  * Copyright (c) 1997 Causality Limited
@@ -39,7 +39,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: footbridge_io.c,v 1.16 2009/12/15 21:38:20 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: footbridge_io.c,v 1.17 2010/11/18 18:06:21 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -210,17 +210,16 @@
 
        /* Now map the pages */
        /* The cookie is the physical base address for the I/O area */
-        for (pa = startpa; pa < endpa; pa+=PAGE_SIZE, va += PAGE_SIZE) 
-        {
-                pmap_enter(pmap_kernel(), va, (bus_addr_t)t + pa, VM_PROT_READ | VM_PROT_WRITE,
-                                VM_PROT_READ | VM_PROT_WRITE| PMAP_WIRED);
-                if ((flags & BUS_SPACE_MAP_CACHEABLE) == 0) {
-                        pt_entry_t *pte;       
-                        pte = vtopte(va);
-                        *pte &= ~L2_S_CACHE_MASK;
-                        PTE_SYNC(pte);
-                }
-        }
+       for (pa = startpa; pa < endpa; pa+=PAGE_SIZE, va += PAGE_SIZE) {
+               pmap_enter(pmap_kernel(), va, (bus_addr_t)t + pa, VM_PROT_READ | VM_PROT_WRITE,
+                   VM_PROT_READ | VM_PROT_WRITE| PMAP_WIRED);
+               if ((flags & BUS_SPACE_MAP_CACHEABLE) == 0) {
+                       pt_entry_t *pte;        
+                       pte = vtopte(va);
+                       *pte &= ~L2_S_CACHE_MASK;
+                       PTE_SYNC(pte);
+               }
+       }
        pmap_update(pmap_kernel());
 
 /*     if (bpa >= DC21285_PCI_MEM_VSIZE && bpa != DC21285_ARMCSR_VBASE)