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[src/trunk]: src/sys/arch/alpha/alpha - don't clear the flags twice in the loop



details:   https://anonhg.NetBSD.org/src/rev/44061bd09243
branches:  trunk
changeset: 771465:44061bd09243
user:      christos <christos%NetBSD.org@localhost>
date:      Mon Nov 21 19:50:37 2011 +0000

description:
- don't clear the flags twice in the loop
- reorder calculation to preserve as much precision as possible.

diffstat:

 sys/arch/alpha/alpha/mcclock.c |  11 ++++++-----
 1 files changed, 6 insertions(+), 5 deletions(-)

diffs (41 lines):

diff -r 0aaa69551718 -r 44061bd09243 sys/arch/alpha/alpha/mcclock.c
--- a/sys/arch/alpha/alpha/mcclock.c    Mon Nov 21 18:29:22 2011 +0000
+++ b/sys/arch/alpha/alpha/mcclock.c    Mon Nov 21 19:50:37 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mcclock.c,v 1.17 2011/07/01 19:22:35 dyoung Exp $ */
+/* $NetBSD: mcclock.c,v 1.18 2011/11/21 19:50:37 christos Exp $ */
 
 /*
  * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
@@ -29,7 +29,7 @@
 
 #include <sys/cdefs.h>                 /* RCS ID & Copyright macro defns */
 
-__KERNEL_RCSID(0, "$NetBSD: mcclock.c,v 1.17 2011/07/01 19:22:35 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mcclock.c,v 1.18 2011/11/21 19:50:37 christos Exp $");
 
 #include "opt_clock_compat_osf1.h"
 
@@ -102,10 +102,11 @@
        /* set interval 16Hz to measure pcc */
        (*sc->sc_mcwrite)(sc, MC_REGA, MC_BASE_32_KHz | MC_RATE_16_Hz);
 
+       /* clear interrupt flags */
+       (void)(*sc->sc_mcread)(sc, MC_REGC);
+
        /* Run the loop an extra time to prime the cache. */
        for (i = 0; i < NLOOP; i++) {
-               /* clear interrupt flags */
-               (void)(*sc->sc_mcread)(sc, MC_REGC);
 
                /* wait till the periodic interrupt flag is set */
                while (((*sc->sc_mcread)(sc, MC_REGC) & MC_REGC_PF) == 0)
@@ -120,7 +121,7 @@
                ctrdiff[i] = pcc_end - pcc_start;
        }
 
-       freq = ((ctrdiff[NLOOP - 2] + ctrdiff[NLOOP - 1]) / 2) * 16 /* Hz */;
+       freq = ((ctrdiff[NLOOP - 2] + ctrdiff[NLOOP - 1]) * 16 /* Hz */) / 2;
 
        /* restore REG_A */
        (*sc->sc_mcwrite)(sc, MC_REGA, reg_a);



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