[src/trunk]: src/sys/arch/mips/mips - use correct ASID bits in MIPS_COP_0_TLB_HI

[tsutsui <tsutsui%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/2c7bece2af0c
branches:  trunk
changeset: 772195:2c7bece2af0c
user:      tsutsui <tsutsui%NetBSD.org@localhost>
date:      Fri Dec 23 10:01:33 2011 +0000

description:
- use correct ASID bits in MIPS_COP_0_TLB_HI
- save/restore current PID in tlb_invalidate_all() and cpu_switch_resume()
  as mipsX_subr.S does

diffstat:

 sys/arch/mips/mips/locore_mips1.S |  18 +++++++++++++-----
 1 files changed, 13 insertions(+), 5 deletions(-)

diffs (67 lines):

diff -r 881eef2a96f5 -r 2c7bece2af0c sys/arch/mips/mips/locore_mips1.S
--- a/sys/arch/mips/mips/locore_mips1.S Fri Dec 23 05:06:19 2011 +0000
+++ b/sys/arch/mips/mips/locore_mips1.S Fri Dec 23 10:01:33 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore_mips1.S,v 1.82 2011/05/07 19:15:48 tsutsui Exp $        */
+/*     $NetBSD: locore_mips1.S,v 1.83 2011/12/23 10:01:33 tsutsui Exp $        */
 
 /*
  * Copyright (c) 1992, 1993
@@ -1265,7 +1265,8 @@
 
        mfc0    ta0, MIPS_COP_0_TLB_HI          # get va and ASID
        nop
-       and     ta0, ta0, PG_ASID               # mask off ASID
+       and     ta0, MIPS1_TLB_PID              # mask off ASID
+       srl     ta0, MIPS1_TLB_PID_SHIFT
        sltu    ta1, ta0, a0                    # < asid_lo
        bnez    ta1, 2f                         # yes, next tlb entry
         nop
@@ -1299,7 +1300,8 @@
        mfc0    v1, MIPS_COP_0_STATUS           # save the status register.
        mtc0    zero, MIPS_COP_0_STATUS         # disable interrupts
 
-       li      t1, MIPS_KSEG0_START
+       mfc0    t0, MIPS_COP_0_TLB_HI           # save current PID
+       li      t1, MIPS_KSEG0_START            # invalid address
        mtc0    t1, MIPS_COP_0_TLB_HI           # make entryHi invalid
        mtc0    zero, MIPS_COP_0_TLB_LOW        # zero out entryLo
 
@@ -1313,6 +1315,7 @@
        bne     t1, a0, 1b
         tlbwi                                  # invalidate the entry
 
+       mtc0    t0, MIPS_COP_0_TLB_HI           # restore PID
        j       ra
         mtc0   v1, MIPS_COP_0_STATUS           # restore status register
 END(MIPSX(tlb_invalidate_all))
@@ -1350,8 +1353,9 @@
 
        mfc0    t0, MIPS_COP_0_TLB_HI           # get va and ASID
        nop
-       and     t0, PG_ASID                     # mask off ASID
-       srl     t0, MIPS1_TLB_INDEX_SHIFT       # shift to low bits
+       and     t0, MIPS1_TLB_PID
+       srl     t0, MIPS1_TLB_PID_SHIFT         # shift to low bits
+       and     t0, a1                          # focus on asid_mask
 
        srl     a2, t0, 3 + LONG_SCALESHIFT     # drop low 5 bits
        sll     a2, LONG_SCALESHIFT             # make an index for the bitmap
@@ -1545,6 +1549,8 @@
        blt     s0, s2, resume
        nop
 
+       mfc0    t3, MIPS_COP_0_TLB_HI           # save PID
+       nop
        mtc0    s0, MIPS_COP_0_TLB_HI           # VPN = va
        nop
        tlbp                                    # probe 1st VPN
@@ -1586,6 +1592,8 @@
        mtc0    a2, MIPS_COP_0_TLB_LOW          # 2nd PFN w/ PG_G
        nop
        tlbwi                                   # set TLB entry #1
+       nop
+       mfc0    t3, MIPS_COP_0_TLB_HI           # restore PID
 
 resume:
        j       ra