[src/trunk]: src/sys/arch/x86/include Add latest CR4 bits:

[jym <jym%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/663e51ec2bf6
branches:  trunk
changeset: 779123:663e51ec2bf6
user:      jym <jym%NetBSD.org@localhost>
date:      Sat May 05 15:08:29 2012 +0000

description:
Add latest CR4 bits:
- CR4_VMXE: VMX operations, used for hardware virtualization.
- CR4_SMXE: SMX operations, used for safer Mode Extensions (ground for
            Intel's TXT - Trusted Execution Technology - platform).
- CR4_FSGSBASE: enable *FSBASE and *GSBASE instructions, for R/W access
                to FS/GS segment base addresses.
- CR4_PCIDE: enable Process Context IDentifiers (other architectures may call
             these "address space identifiers").
- CR4_OSXSAVE: enable xsave and xrestore instructions
- CR4_SMEP: Supervisor Mode Execution Prevention. Allows enforcing --x rights
            from cpl 0.

>From Intel? 64 and IA-32 Architectures Software Developer?s Manual,
March 2012.

Align declarations.

CPUID_* bits for these features follow.

diffstat:

 sys/arch/x86/include/specialreg.h |  32 +++++++++++++++++++-------------
 1 files changed, 19 insertions(+), 13 deletions(-)

diffs (48 lines):

diff -r 7b3cba8b104e -r 663e51ec2bf6 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Sat May 05 15:04:57 2012 +0000
+++ b/sys/arch/x86/include/specialreg.h Sat May 05 15:08:29 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.58 2012/04/30 00:04:31 christos Exp $ */
+/*     $NetBSD: specialreg.h,v 1.59 2012/05/05 15:08:29 jym Exp $      */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -68,20 +68,26 @@
 /* the remaining 7 bits of this register are reserved */
 
 /*
- * bits in the pentiums %cr4 register:
+ * bits in the %cr4 control register:
  */
+#define CR4_VME                0x00000001 /* virtual 8086 mode extension enable */
+#define CR4_PVI                0x00000002 /* protected mode virtual interrupt enable */
+#define CR4_TSD                0x00000004 /* restrict RDTSC instruction to cpl 0 */
+#define CR4_DE         0x00000008 /* debugging extension */
+#define CR4_PSE                0x00000010 /* large (4MB) page size enable */
+#define CR4_PAE                0x00000020 /* physical address extension enable */
+#define CR4_MCE                0x00000040 /* machine check enable */
+#define CR4_PGE                0x00000080 /* page global enable */
+#define CR4_PCE                0x00000100 /* enable RDPMC instruction for all cpls */
+#define CR4_OSFXSR     0x00000200 /* enable fxsave/fxrestor and SSE */
+#define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
+#define CR4_VMXE       0x00002000 /* enable VMX operations */
+#define CR4_SMXE       0x00004000 /* enable SMX operations */
+#define CR4_FSGSBASE   0x00010000 /* enable *FSBASE and *GSBASE instructions */
+#define CR4_PCIDE      0x00020000 /* enable Process Context IDentifiers */
+#define CR4_OSXSAVE    0x00040000 /* enable xsave and xrestore */
+#define CR4_SMEP       0x00100000 /* enable SMEP support */
 
-#define CR4_VME        0x00000001      /* virtual 8086 mode extension enable */
-#define CR4_PVI 0x00000002     /* protected mode virtual interrupt enable */
-#define CR4_TSD 0x00000004     /* restrict RDTSC instruction to cpl 0 only */
-#define CR4_DE 0x00000008      /* debugging extension */
-#define CR4_PSE        0x00000010      /* large (4MB) page size enable */
-#define CR4_PAE 0x00000020     /* physical address extension enable */
-#define CR4_MCE        0x00000040      /* machine check enable */
-#define CR4_PGE        0x00000080      /* page global enable */
-#define CR4_PCE        0x00000100      /* enable RDPMC instruction for all cpls */
-#define CR4_OSFXSR     0x00000200      /* enable fxsave/fxrestor and SSE */
-#define CR4_OSXMMEXCPT 0x00000400      /* enable unmasked SSE exceptions */
 
 /*
  * CPUID "features" bits