[src/trunk]: src/sys/arch/sparc64/include add some defines for the sizes of T...

[mrg <mrg%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/3cb2e8489d0f
branches:  trunk
changeset: 752082:3cb2e8489d0f
user:      mrg <mrg%NetBSD.org@localhost>
date:      Sat Feb 13 08:46:23 2010 +0000

description:
add some defines for the sizes of TLBs in various CPUs.

diffstat:

 sys/arch/sparc64/include/ctlreg.h |  13 ++++++++++++-
 1 files changed, 12 insertions(+), 1 deletions(-)

diffs (27 lines):

diff -r 6c6aa9d98eec -r 3cb2e8489d0f sys/arch/sparc64/include/ctlreg.h
--- a/sys/arch/sparc64/include/ctlreg.h Sat Feb 13 07:48:01 2010 +0000
+++ b/sys/arch/sparc64/include/ctlreg.h Sat Feb 13 08:46:23 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ctlreg.h,v 1.49 2010/02/01 06:26:15 mrg Exp $ */
+/*     $NetBSD: ctlreg.h,v 1.50 2010/02/13 08:46:23 mrg Exp $ */
 
 /*
  * Copyright (c) 1996-2002 Eduardo Horvath
@@ -365,6 +365,17 @@
 #define        DEMAP_ALL                       ((0x08)<<4)     /* Demap all non-locked TLB entries [USIII] */
 
 /*
+ * These define the sizes of the TLB in various CPUs.
+ * They're mostly not necessary except for diagnostic code.
+ */
+#define TLB_SIZE_SPITFIRE              64
+#define TLB_SIZE_CHEETAH_I16           16
+#define TLB_SIZE_CHEETAH_I128          128
+#define TLB_SIZE_CHEETAH_D16           16
+#define TLB_SIZE_CHEETAH_D512_0                512
+#define TLB_SIZE_CHEETAH_D512_1                512
+
+/*
  * Interrupt registers.  This really gets hairy.
  */