[src/netbsd-6]: src/sys/arch/x86 Pull up following revision(s) (requested by ...

[riz <riz%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/ba2a5051d5b9
branches:  netbsd-6
changeset: 774061:ba2a5051d5b9
user:      riz <riz%NetBSD.org@localhost>
date:      Mon May 07 16:37:19 2012 +0000

description:
Pull up following revision(s) (requested by christos in ticket #220):
        sys/arch/x86/x86/identcpu.c: revision 1.31
        sys/arch/x86/include/specialreg.h: revision 1.58
PR/41267: Andrius V: 5.0 RC4 does not detect second CPU in VIA. VIA Eden cpuid
lies about it's ability to do cmpxchg8b. Turn the feature on using the FCR MSR.
Needs pullup to both 5 and 6.
Add VIA Eden FCR MSR.

diffstat:

 sys/arch/x86/include/specialreg.h |   7 ++++++-
 sys/arch/x86/x86/identcpu.c       |  30 ++++++++++++++++++++++++------
 2 files changed, 30 insertions(+), 7 deletions(-)

diffs (75 lines):

diff -r 5cd1fdaea03a -r ba2a5051d5b9 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Mon May 07 16:31:11 2012 +0000
+++ b/sys/arch/x86/include/specialreg.h Mon May 07 16:37:19 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.55.2.2 2012/04/09 18:02:24 riz Exp $  */
+/*     $NetBSD: specialreg.h,v 1.55.2.3 2012/05/07 16:37:19 riz Exp $  */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -445,6 +445,11 @@
 #define MSR_VIA_ACE_ENABLE     0x10000000
 
 /*
+ * VIA "Eden" MSRs
+ */
+#define MSR_VIA_FCR            MSR_VIA_ACE
+
+/*
  * AMD K6/K7 MSRs.
  */
 #define        MSR_K6_UWCCR            0xc0000085
diff -r 5cd1fdaea03a -r ba2a5051d5b9 sys/arch/x86/x86/identcpu.c
--- a/sys/arch/x86/x86/identcpu.c       Mon May 07 16:31:11 2012 +0000
+++ b/sys/arch/x86/x86/identcpu.c       Mon May 07 16:37:19 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: identcpu.c,v 1.29.2.1 2012/02/23 18:37:31 riz Exp $    */
+/*     $NetBSD: identcpu.c,v 1.29.2.2 2012/05/07 16:37:19 riz Exp $    */
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.29.2.1 2012/02/23 18:37:31 riz Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.29.2.2 2012/05/07 16:37:19 riz Exp $");
 
 #include "opt_xen.h"
 
@@ -380,13 +380,31 @@
 cpu_probe_winchip(struct cpu_info *ci)
 {
 
-       if (cpu_vendor != CPUVENDOR_IDT ||
-           CPUID2FAMILY(ci->ci_signature) != 5)
+       if (cpu_vendor != CPUVENDOR_IDT)
                return;
 
-       if (CPUID2MODEL(ci->ci_signature) == 4) {
+       switch (CPUID2FAMILY(ci->ci_signature)) {
+       case 5:
                /* WinChip C6 */
-               ci->ci_feat_val[0] &= ~CPUID_TSC;
+               if (CPUID2MODEL(ci->ci_signature) == 4)
+                       ci->ci_feat_val[0] &= ~CPUID_TSC;
+               break;
+       case 6:
+               /*
+                * VIA Eden ESP 
+                *
+                * Quoting from page 3-4 of: "VIA Eden ESP Processor Datasheet"
+                * http://www.via.com.tw/download/mainboards/6/14/Eden20v115.pdf
+                * 
+                * 1. The CMPXCHG8B instruction is provided and always enabled,
+                *    however, it appears disabled in the corresponding CPUID
+                *    function bit 0 to avoid a bug in an early version of
+                *    Windows NT. However, this default can be changed via a
+                *    bit in the FCR MSR.
+                */
+               ci->ci_feat_val[0] |= CPUID_CX8;
+               wrmsr(MSR_VIA_FCR, rdmsr(MSR_VIA_FCR) | 0x00000001);
+               break;
        }
 }