[src/trunk]: src/sys/arch/amd64/amd64 Enable the NX bit feature early in the ...

[jym <jym%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/822b28de0817
branches:  trunk
changeset: 754107:822b28de0817
user:      jym <jym%NetBSD.org@localhost>
date:      Tue Apr 20 15:42:21 2010 +0000

description:
Enable the NX bit feature early in the MP trampoline code (do not rely on
cpu_init_msrs() to do it). Having NX bit set on a page will raise a #GP
on fetch if NXE is not enabled, which can happen early when structures
(like idlelwp) are allocated with just rw- rights.

diffstat:

 sys/arch/amd64/amd64/mptramp.S |  15 +++++++++++++--
 1 files changed, 13 insertions(+), 2 deletions(-)

diffs (36 lines):

diff -r 7d3151d2a368 -r 822b28de0817 sys/arch/amd64/amd64/mptramp.S
--- a/sys/arch/amd64/amd64/mptramp.S    Tue Apr 20 14:32:03 2010 +0000
+++ b/sys/arch/amd64/amd64/mptramp.S    Tue Apr 20 15:42:21 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mptramp.S,v 1.11 2010/04/18 23:47:50 jym Exp $ */
+/*     $NetBSD: mptramp.S,v 1.12 2010/04/20 15:42:21 jym Exp $ */
 
 /*-
  * Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -216,6 +216,18 @@
 
        
 _C_LABEL(cpu_spinup_trampoline_end):   #end of code copied to MP_TRAMPOLINE
+       /*
+        * If EFER_NXE is not enabled, fetching a page with a NX bit set
+        * will raise a #GP. Avoid that by setting the NXE feature now.
+        */
+       movl    _C_LABEL(cpu_feature)+2*4,%eax  /* cpu_feature[2] */
+       andl    $CPUID_NOX,%eax
+       jz      1f
+       movl    $MSR_EFER,%ecx
+       rdmsr
+       orl     $EFER_NXE,%eax  /* enable No-Execute feature */
+       wrmsr
+
 1:
        /* Don't touch lapic until BP has done init sequence. */
        movq    _C_LABEL(cpu_starting),%rdi
@@ -223,7 +235,6 @@
        testq   %rdi, %rdi
        jz      1b
 
-1:
        movq    CPU_INFO_IDLELWP(%rdi),%rsi
        movq    L_PCB(%rsi),%rsi