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[src/trunk]: src/sys/arch/evbarm/bcm53xx Use the common code in <arm/cortex/a...
details: https://anonhg.NetBSD.org/src/rev/526ccc02205f
branches: trunk
changeset: 781369:526ccc02205f
user: matt <matt%NetBSD.org@localhost>
date: Sun Sep 02 05:02:36 2012 +0000
description:
Use the common code in <arm/cortex/a9_mpsubr.S>
diffstat:
sys/arch/evbarm/bcm53xx/bcm53xx_start.S | 429 ++-----------------------------
1 files changed, 37 insertions(+), 392 deletions(-)
diffs (truncated from 497 to 300 lines):
diff -r 954a68944b9d -r 526ccc02205f sys/arch/evbarm/bcm53xx/bcm53xx_start.S
--- a/sys/arch/evbarm/bcm53xx/bcm53xx_start.S Sun Sep 02 05:01:54 2012 +0000
+++ b/sys/arch/evbarm/bcm53xx/bcm53xx_start.S Sun Sep 02 05:02:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm53xx_start.S,v 1.1 2012/09/01 00:15:11 matt Exp $ */
+/* $NetBSD: bcm53xx_start.S,v 1.2 2012/09/02 05:02:36 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -41,15 +41,20 @@
#include <arm/cortex/a9tmr_reg.h>
-RCSID("$NetBSD: bcm53xx_start.S,v 1.1 2012/09/01 00:15:11 matt Exp $")
+#ifndef CONADDR
+#define CONADDR 0x18000300
+#endif
+
+RCSID("$NetBSD: bcm53xx_start.S,v 1.2 2012/09/02 05:02:36 matt Exp $")
#undef VERBOSE_INIT_ARM
#define VERBOSE_INIT_ARM
#if defined(VERBOSE_INIT_ARM)
-#define PUTC(n) mov r0, n; bl xputc
+#define XPUTC(n) mov r0, n; bl xputc
+#define XPUTC_COM 1
#else
-#define PUTC(n)
+#define XPUTC(n)
#endif
/*
@@ -61,150 +66,55 @@
.global _C_LABEL(bcm53xx_start)
_C_LABEL(bcm53xx_start):
- cpsid if, #PSR_SVC32_MODE
-
- PUTC(#64)
- bl _C_LABEL(armv7_icache_inv_all) @ invalidate i-cache
-
/*
- * Step 1a, invalidate the all cache tags in all ways on the SCU.
+ * Let's turn on the CCA watchdog in case something goes horribly wrong.
*/
- PUTC(#65)
- mrc p15, 4, r3, c15, c0, 0 @ read cbar
-
- mrc p15, 0, r0, c0, c0, 5 @ get MPIDR
- and r0, r0, #7 @ get our cpu numder
- lsl r0, r0, #2 @ multiply by 4
- mov r1, #0xf @ select all ways
- lsl r1, r1, r0 @ shift into place
- str r1, [r3, #12] @ write scu invalidate all
- dsb
- isb
-
- /*
- * Step 1b, invalidate the data cache
- */
- PUTC(#66)
- bl _C_LABEL(armv7_dcache_wbinv_all) @ writeback/invalidate d-cache
+ ldr r0, .Lcca_wdog
+ ldr r1, .Lcca_wdog + 4
+ str r1, [r0]
/*
- * Step 2, disable the data cache
+ * Cal the initial start code for the a9
*/
- mrc p15, 0, r2, c1, c0, 0 @ get system ctl register (save)
- bic r1, r2, #CPU_CONTROL_DC_ENABLE @ clear data cache enable
- mcr p15, 0, r1, c1, c0, 0 @ set system ctl register
- isb
-
- /*
- * Step 3, enable the SCU (and set SMP mode)
- */
- ldr r1, [r3, #4] @ read scu config
- orr r1, r1, #0xf0 @ set smp mode
- str r1, [r3, #4] @ write scu config
- ldr r1, [r3, #0] @ read scu control
- orr r1, r1, #1 @ set scu enable flag
- str r1, [r3, #4] @ write scu control
- dsb
- isb
+ bl a9_start
/*
- * Step 4a, enable the data cache
- */
- mcr p15, 0, r2, c1, c0, 0 @ reenable caches
- isb
-
- /*
- * Step 4b, set ACTLR.SMP=1 (and ACTRL.FX=1)
- */
- mrc p15, 0, r0, c1, c0, 1 @ read aux ctl
- orr r0, #0x40 @ enable SMP mode
- mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
- isb
- orr r0, #0x1 @ enable cache/tlb/coherency
- mcr p15, 0, r0, c1, c0, 1 @ write aux ctl
- isb
-
- PUTC(#67)
- /*
* Set up a preliminary mapping in the MMU to allow us to run
* at KERNEL_BASE with caches on.
*/
- /* Build page table from scratch */
- ldr r0, .Ltemp_l1_table /* The page table address - entered into TTB later */
- mov r1, r0 /* Start address to clear memory. */
- /* Zero the entire table so all virtual addresses are invalid. */
- mov r2, #L1_TABLE_SIZE /* in bytes */
- mov r3, #0
- mov r4, r3
- mov r5, r3
- mov r6, r3
- mov r7, r3
- mov r8, r3
- mov r10, r3
- mov r11, r3
-1: stmia r1!, {r3-r8,r10-r11}
- stmia r1!, {r3-r8,r10-r11}
- stmia r1!, {r3-r8,r10-r11}
- stmia r1!, {r3-r8,r10-r11}
- subs r2, r2, #(4 * 4 * 8) /* bytes per loop */
- bne 1b
-
- /* Now create our entries per the mmu_init_table. */
- l1table .req r0
- va .req r1
- pa .req r2
- n_sec .req r3
- attr .req r4
- itable .req r5
+ ldr r0, .Ltemp_l1_table /* The L1PT address - entered into TTB later */
+ adr r1, mmu_init_table
+ bl arm_boot_l1pt_init
- adr itable, mmu_init_table
- b 3f
-
-2: str pa, [l1table, va]
- add va, va, #4
- add pa, pa, #(L1_S_SIZE)
- subs n_sec, n_sec, #1
- bhi 2b
-
-3: ldmia itable!, {va,pa,n_sec,attr}
- /* Convert va to l1 offset: va = 4 * (va >> L1_S_SHIFT) */
- lsr va, va, #L1_S_SHIFT
- lsl va, va, #2
- /* Convert pa to l1 entry: pa = (pa & L1_S_FRAME) | attr */
- bfc pa, #0, #L1_S_SHIFT
- orr pa, pa, attr
- cmp n_sec, #0
- bne 2b
-
- .unreq va
- .unreq pa
- .unreq n_sec
- .unreq attr
- .unreq itable
- .unreq l1table
-
- PUTC(#68)
+ XPUTC(#68)
/*
* Before we turn on the MMU, let's the other process out of the
* SKU ROM but setting the magic LUT address to our own mp_start
* routine.
*/
ldr r1, .Lsku_rom_lut
- adr r2, mp_start
+ adr r2, a9_mpstart
str r2, [r1]
sev /* wake up the others */
/*
* init the CPU TLB, Cache, MMU.
*/
- PUTC(#69)
+ XPUTC(#69)
ldr r0, .Ltemp_l1_table /* The page table address */
- bl cpu_init
+ bl a9_cpuinit
+
+ XPUTC(#33)
+ XPUTC(#10)
+ XPUTC(#13)
- PUTC(#33)
- PUTC(#10)
- PUTC(#13)
+ /*
+ * Let's turn off the CCA watchdog since nothing went horribly wrong.
+ */
+ ldr r0, .Lcca_wdog
+ mov r1, #0
+ str r1, [r0]
/*
* Jump to start in locore.S, which in turn will call initarm and main.
@@ -220,44 +130,15 @@
.Lsku_rom_lut:
.word 0xffff0400
+.Lcca_wdog:
+ .word 0x18000080
+ .word 0x0fffffff /* maximum watchdog time out, about 10 seconds */
+
.Ltemp_l1_table:
/* Put the temporary L1 translation table far enough away. */
.word KERNEL_BASE_phys + 31 * 0x100000 - L1_TABLE_SIZE
-
-/*
- * Coprocessor register initialization values
- */
- .p2align 3
- /* bits to clear in the Control Register */
-.Lcontrol_clr:
- .word 0
-
- /* bits to set in the Control Register */
-.Lcontrol_set:
- .word CPU_CONTROL_MMU_ENABLE | \
- CPU_CONTROL_AFLT_ENABLE | \
- CPU_CONTROL_DC_ENABLE | \
- CPU_CONTROL_SYST_ENABLE | \
- CPU_CONTROL_SWP_ENABLE | \
- CPU_CONTROL_IC_ENABLE
-#if 0
- (15 << 3) | /* SBOP */ \
- (1 << 16) | /* SBO */ \
- (1 << 18) | /* SBO */ \
- (3 << 22) /* SB0 */
-#endif
-
- /* bits to disable the caches */
-.Lctl_ID_dis:
- .word ~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
-
-/* We'll modify va and pa at run time so we can use relocatable addresses. */
-#define MMU_INIT(va,pa,n_sec,attr) \
- .word va ; \
- .word pa ; \
- .word n_sec ; \
- .word attr ;
+#include <arm/cortex/a9_mpsubr.S>
mmu_init_table:
/* Add 32MB of VA==PA at 0x80000000 so we can keep the kernel going */
@@ -287,239 +168,3 @@
/* end of table */
MMU_INIT(0, 0, 0, 0)
-
-cpu_init:
- /*
- * In theory, because the MMU is off, we shouldn't need all of this,
- * but let's not take any chances and do a typical sequence to set
- * the Translation Table Base.
- */
- mov ip, lr
- mov r10, r0
- mov r1, #0 /* SBZ */
-
- ldr r3, .Lctl_ID_dis /* Disable I+D caches */
- mrc p15, 0, r2, c1, c0, 0 /* " " " */
- and r2, r2, r3 /* " " " */
- mcr p15, 0, r2, c1, c0, 0 /* " " " */
-
- PUTC(#70)
- mov r1, #0
- mcr p15, 0, r1, c7, c10, 4 /* Drain the write buffers. */
-
- PUTC(#71)
- mcr p15, 0, r10, c2, c0, 0 /* Set Translation Table Base */
-
- PUTC(#72)
- mov r1, #0
- mcr p15, 0, r1, c8, c7, 0 /* Invalidate TLBs */
-
- /* Set the Domain Access register. Very important! */
- PUTC(#74)
- mov r1, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
- mcr p15, 0, r1, c3, c0, 0
-
- /*
- * Enable the MMU, etc.
- */
- PUTC(#75)
- mrc p15, 0, r0, c1, c0, 0
-
- ldr r2, .Lcontrol_clr
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