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[src/trunk]: src/sys/arch/sandpoint/stand/altboot The Apollo family of IDE in...
details: https://anonhg.NetBSD.org/src/rev/572c257bdcf1
branches: trunk
changeset: 770773:572c257bdcf1
user: phx <phx%NetBSD.org@localhost>
date: Tue Nov 01 16:32:57 2011 +0000
description:
The Apollo family of IDE interface chips has both channels disabled by
default, so we have to enable them in a new chipfix function. Also move
the channel enable code for the 82C686B from encpcifix() to pciide.c.
diffstat:
sys/arch/sandpoint/stand/altboot/brdsetup.c | 34 +++++++++------------------
sys/arch/sandpoint/stand/altboot/dsk.c | 4 ++-
sys/arch/sandpoint/stand/altboot/pciide.c | 35 ++++++++++++++++++++++------
3 files changed, 42 insertions(+), 31 deletions(-)
diffs (178 lines):
diff -r 75b924db7527 -r 572c257bdcf1 sys/arch/sandpoint/stand/altboot/brdsetup.c
--- a/sys/arch/sandpoint/stand/altboot/brdsetup.c Tue Nov 01 15:39:37 2011 +0000
+++ b/sys/arch/sandpoint/stand/altboot/brdsetup.c Tue Nov 01 16:32:57 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: brdsetup.c,v 1.19 2011/10/30 21:08:33 phx Exp $ */
+/* $NetBSD: brdsetup.c,v 1.20 2011/11/01 16:32:57 phx Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
@@ -454,25 +454,20 @@
/*
* //// IDE fixup ////
* - "native mode" (ide 0x09)
- * - use primary only (ide 0x40)
*/
+
/* ide: 0x09 - programming interface; 1000'SsPp */
val = pcicfgread(ide, 0x08) & 0xffff00ff;
pcicfgwrite(ide, 0x08, val | (0x8f << 8));
/* ide: 0x10-20 - leave them PCI memory space assigned */
-
- /* ide: 0x40 - use primary only */
- val = pcicfgread(ide, 0x40) &~ 03;
- val |= 02;
- pcicfgwrite(ide, 0x40, val);
#else
/*
* //// IDE fixup ////
* - "compatiblity mode" (ide 0x09)
- * - use primary only (ide 0x40)
* - remove PCI pin assignment (ide 0x3d)
*/
+
/* ide: 0x09 - programming interface; 1000'SsPp */
val = pcicfgread(ide, 0x08) & 0xffff00ff;
val |= (0x8a << 8);
@@ -480,22 +475,17 @@
/* ide: 0x10-20 */
/*
- experiment shows writing ide: 0x09 changes these
- register behaviour. The pcicfgwrite() above writes
- 0x8a at ide: 0x09 to make sure legacy IDE. Then
- reading BAR0-3 is to return value 0s even though
- pcisetup() has written range assignments. Value
- overwrite makes no effect. Having 0x8f for native
- PCIIDE doesn't change register values and brings no
- weirdness.
+ * experiment shows writing ide: 0x09 changes these
+ * register behaviour. The pcicfgwrite() above writes
+ * 0x8a at ide: 0x09 to make sure legacy IDE. Then
+ * reading BAR0-3 is to return value 0s even though
+ * pcisetup() has written range assignments. Value
+ * overwrite makes no effect. Having 0x8f for native
+ * PCIIDE doesn't change register values and brings no
+ * weirdness.
*/
- /* ide: 0x40 - use primary only */
- val = pcicfgread(ide, 0x40) &~ 03;
- val |= 02;
- pcicfgwrite(ide, 0x40, val);
-
- /* ide: 0x3d/3c - turn off PCI pin */
+ /* ide: 0x3d/3c - turn off PCI pin */
val = pcicfgread(ide, 0x3c) & 0xffff00ff;
pcicfgwrite(ide, 0x3c, val);
#endif
diff -r 75b924db7527 -r 572c257bdcf1 sys/arch/sandpoint/stand/altboot/dsk.c
--- a/sys/arch/sandpoint/stand/altboot/dsk.c Tue Nov 01 15:39:37 2011 +0000
+++ b/sys/arch/sandpoint/stand/altboot/dsk.c Tue Nov 01 16:32:57 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dsk.c,v 1.9 2011/10/30 21:08:33 phx Exp $ */
+/* $NetBSD: dsk.c,v 1.10 2011/11/01 16:32:57 phx Exp $ */
/*-
* Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -102,6 +102,8 @@
return 0;
found:
pci->drv = (*dv->init)(tag, NULL);
+ if (pci->drv == NULL)
+ return 0;
disk_scan(pci->drv);
return 1;
}
diff -r 75b924db7527 -r 572c257bdcf1 sys/arch/sandpoint/stand/altboot/pciide.c
--- a/sys/arch/sandpoint/stand/altboot/pciide.c Tue Nov 01 15:39:37 2011 +0000
+++ b/sys/arch/sandpoint/stand/altboot/pciide.c Tue Nov 01 16:32:57 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pciide.c,v 1.7 2011/04/25 18:30:18 phx Exp $ */
+/* $NetBSD: pciide.c,v 1.8 2011/11/01 16:32:57 phx Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
@@ -36,6 +36,7 @@
#include "globals.h"
static int cmdidefix(struct dkdev_ata *);
+static int apoidefix(struct dkdev_ata *);
static uint32_t pciiobase = PCI_XIOBASE;
@@ -45,6 +46,7 @@
};
static struct myops defaultops = { NULL, NULL };
static struct myops cmdideops = { cmdidefix, NULL };
+static struct myops apoideops = { apoidefix, NULL };
static struct myops *myops;
int
@@ -57,9 +59,12 @@
case PCI_DEVICE(0x1095, 0x0680): /* SiI 0680 IDE */
myops = &cmdideops;
return 1;
- case PCI_DEVICE(0x1283, 0x8211): /* ITE 8211 IDE */
+ case PCI_DEVICE(0x1106, 0x0571): /* VIA 82C586A IDE */
case PCI_DEVICE(0x1106, 0x1571): /* VIA 82C586 IDE */
- case PCI_DEVICE(0x1106, 0x3164): /* VIA VT6410 */
+ case PCI_DEVICE(0x1106, 0x3164): /* VIA VT6410 RAID IDE */
+ myops = &apoideops;
+ return 1;
+ case PCI_DEVICE(0x1283, 0x8211): /* ITE 8211 IDE */
case PCI_DEVICE(0x10ad, 0x0105): /* Symphony Labs 82C105 IDE */
case PCI_DEVICE(0x10b8, 0x5229): /* ALi IDE */
case PCI_DEVICE(0x1191, 0x0008): /* ACARD ATP865 */
@@ -82,9 +87,15 @@
l->iobuf = allocaligned(512, 16);
l->tag = tag;
+ /* chipset specific fixes */
+ if (myops->chipfix)
+ if (!(*myops->chipfix)(l))
+ return NULL;
+
val = pcicfgread(tag, PCI_CLASS_REG);
native = PCI_CLASS(val) != PCI_CLASS_IDE ||
(PCI_INTERFACE(val) & 05) != 0;
+
if (native) {
/* native, use BAR 01234 */
l->bar[0] = pciiobase + (pcicfgread(tag, 0x10) &~ 01);
@@ -124,17 +135,13 @@
printf("channel %d present\n", n);
}
- /* make sure to have PIO0 */
- if (myops->chipfix)
- (*myops->chipfix)(l);
-
return l;
}
static int
cmdidefix(struct dkdev_ata *l)
{
- int v;
+ unsigned v;
v = pcicfgread(l->tag, 0x80);
pcicfgwrite(l->tag, 0x80, (v & ~0xff) | 0x01);
@@ -147,3 +154,15 @@
return 1;
}
+
+static int
+apoidefix(struct dkdev_ata *l)
+{
+ unsigned v;
+
+ /* enable primary and secondary channel */
+ v = pcicfgread(l->tag, 0x40) & ~0x03;
+ pcicfgwrite(l->tag, 0x40, v | 0x03);
+
+ return 1;
+}
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