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[src/netbsd-6]: src/sys/arch/arm/arm Pull up following revision(s) (requested...
details: https://anonhg.NetBSD.org/src/rev/8ad5a58dcb73
branches: netbsd-6
changeset: 775614:8ad5a58dcb73
user: riz <riz%NetBSD.org@localhost>
date: Mon Jan 07 16:42:51 2013 +0000
description:
Pull up following revision(s) (requested by msaitoh in ticket #774):
sys/arch/arm/arm/cpufunc.c: revision 1.119
Enable DCache Streaming Switch and Write Allocate.
This change improve system performance significantly.
diffstat:
sys/arch/arm/arm/cpufunc.c | 14 ++++++++++++--
1 files changed, 12 insertions(+), 2 deletions(-)
diffs (42 lines):
diff -r b65187a2ebea -r 8ad5a58dcb73 sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c Mon Jan 07 15:54:00 2013 +0000
+++ b/sys/arch/arm/arm/cpufunc.c Mon Jan 07 16:42:51 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.104.2.1 2012/08/09 06:36:44 jdc Exp $ */
+/* $NetBSD: cpufunc.c,v 1.104.2.2 2013/01/07 16:42:51 riz Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.104.2.1 2012/08/09 06:36:44 jdc Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.104.2.2 2013/01/07 16:42:51 riz Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -3352,6 +3352,7 @@
sheeva_setup(char *args)
{
int cpuctrl, cpuctrlmask;
+ uint32_t sheeva_ext;
cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
@@ -3369,6 +3370,15 @@
cpuctrl = parse_cpu_options(args, sheeva_options, cpuctrl);
+ /* Enable DCache Streaming Switch and Write Allocate */
+ __asm volatile("mrc p15, 1, %0, c15, c1, 0"
+ : "=r" (sheeva_ext));
+
+ sheeva_ext |= FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN;
+
+ __asm volatile("mcr p15, 1, %0, c15, c1, 0"
+ :: "r" (sheeva_ext));
+
/*
* Sheeva has L2 Cache. Enable/Disable it here.
* Really not support yet...
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