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[src/trunk]: src/sys Add nside(4) - a driver for the National Semiconductor P...
details: https://anonhg.NetBSD.org/src/rev/32c256f0aa0d
branches: trunk
changeset: 758603:32c256f0aa0d
user: skrll <skrll%NetBSD.org@localhost>
date: Wed Nov 10 22:34:24 2010 +0000
description:
Add nside(4) - a driver for the National Semiconductor PC87415 IDE
controller as found in many HP PA-RISC machines.
>From OpenBSD.
Reviewed by Manuel Bouyer.
diffstat:
sys/arch/hp700/conf/GENERIC | 5 +-
sys/dev/pci/files.pci | 7 +-
sys/dev/pci/nside.c | 260 +++++++++++++++++++++++++++++++++++++++
sys/dev/pci/pciide_natsemi_reg.h | 107 ++++++++++++++++
4 files changed, 376 insertions(+), 3 deletions(-)
diffs (truncated from 422 to 300 lines):
diff -r 2f983b874416 -r 32c256f0aa0d sys/arch/hp700/conf/GENERIC
--- a/sys/arch/hp700/conf/GENERIC Wed Nov 10 18:56:17 2010 +0000
+++ b/sys/arch/hp700/conf/GENERIC Wed Nov 10 22:34:24 2010 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.103 2010/11/09 12:24:47 skrll Exp $
+# $NetBSD: GENERIC,v 1.104 2010/11/10 22:34:24 skrll Exp $
#
# GENERIC machine description file
#
@@ -23,7 +23,7 @@
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
options SYSCTL_INCLUDE_DESCR # Include sysctl descriptions in kernel
-#ident "GENERIC-$Revision: 1.103 $"
+#ident "GENERIC-$Revision: 1.104 $"
maxusers 32 # estimated number of users
@@ -416,6 +416,7 @@
cypide* at pci? dev ? function ? # Cypress IDE controllers
geodeide* at pci? dev ? function ? # AMD Geode IDE controllers
hptide* at pci? dev ? function ? # Triones/HighPoint IDE controllers
+nside* at pci? dev ? function ? # National Semiconductor IDE controllers
optiide* at pci? dev ? function ? # Opti IDE controllers
pdcide* at pci? dev ? function ? # Promise IDE controllers
pdcsata* at pci? dev ? function ? # Promise SATA150 controllers
diff -r 2f983b874416 -r 32c256f0aa0d sys/dev/pci/files.pci
--- a/sys/dev/pci/files.pci Wed Nov 10 18:56:17 2010 +0000
+++ b/sys/dev/pci/files.pci Wed Nov 10 22:34:24 2010 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.pci,v 1.332 2010/11/09 12:24:48 skrll Exp $
+# $NetBSD: files.pci,v 1.333 2010/11/10 22:34:24 skrll Exp $
#
# Config file and device description for machine-independent PCI code.
# Included by ports that need it. Requires that the SCSI files be
@@ -274,6 +274,11 @@
attach ahcisata at jmide_hl with jmahci
file dev/pci/jmide.c jmide | jmahci needs-flag
+# National Semiconductor IDE controllers
+device nside: ata, ata_dma, ata_udma, pciide_common, wdc_common
+attach nside at pci
+file dev/pci/nside.c nside
+
# Opti IDE controllers
device optiide: ata, ata_dma, pciide_common, wdc_common
attach optiide at pci
diff -r 2f983b874416 -r 32c256f0aa0d sys/dev/pci/nside.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/dev/pci/nside.c Wed Nov 10 22:34:24 2010 +0000
@@ -0,0 +1,260 @@
+/* $NetBSD: nside.c,v 1.1 2010/11/10 22:34:24 skrll Exp $ */
+
+/*
+ * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: nside.c,v 1.1 2010/11/10 22:34:24 skrll Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+#include <dev/pci/pciidereg.h>
+#include <dev/pci/pciidevar.h>
+#include <dev/pci/pciide_natsemi_reg.h>
+
+static void natsemi_chip_map(struct pciide_softc*, struct pci_attach_args*);
+static void natsemi_setup_channel(struct ata_channel*);
+static int natsemi_pci_intr(void *);
+static void natsemi_irqack(struct ata_channel *);
+
+static int nside_match(device_t, cfdata_t, void *);
+static void nside_attach(device_t, device_t, void *);
+
+struct nside_softc {
+ struct pciide_softc pciide_sc;
+ struct pci_attach_args pcib_pa;
+};
+
+CFATTACH_DECL_NEW(nside, sizeof(struct nside_softc),
+ nside_match, nside_attach, NULL, NULL);
+
+static const struct pciide_product_desc pciide_natsemi_products[] = {
+ { PCI_PRODUCT_NS_PC87415, /* National Semi PC87415 IDE */
+ 0,
+ "National Semiconductor PC87415 IDE Controller",
+ natsemi_chip_map,
+ },
+ { 0,
+ 0,
+ NULL,
+ NULL
+ }
+};
+
+static int
+nside_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct pci_attach_args *pa = aux;
+
+ if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS &&
+ PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
+ PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
+ if (pciide_lookup_product(pa->pa_id, pciide_natsemi_products))
+ return 2;
+ }
+ return 0;
+}
+
+static void
+nside_attach(device_t parent, device_t self, void *aux)
+{
+ struct pci_attach_args *pa = aux;
+ struct pciide_softc *sc = device_private(self);
+
+ sc->sc_wdcdev.sc_atac.atac_dev = self;
+
+ pciide_common_attach(sc, pa,
+ pciide_lookup_product(pa->pa_id, pciide_natsemi_products));
+}
+
+static void
+natsemi_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
+{
+ struct pciide_channel *cp;
+ int channel;
+ pcireg_t interface, ctl;
+
+ if (pciide_chipen(sc, pa) == 0)
+ return;
+
+ aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
+ "bus-master DMA support present");
+ pciide_mapreg_dma(sc, pa);
+ aprint_verbose("\n");
+
+ sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
+
+ if (sc->sc_dma_ok) {
+ sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
+ sc->sc_wdcdev.irqack = natsemi_irqack;
+ }
+
+ pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CCBT, 0xb7);
+
+ /*
+ * Mask off interrupts from both channels, appropriate channel(s)
+ * will be unmasked later.
+ */
+ pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2,
+ pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) |
+ NATSEMI_CHMASK(0) | NATSEMI_CHMASK(1));
+
+ sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
+ sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
+ sc->sc_wdcdev.sc_atac.atac_set_modes = natsemi_setup_channel;
+ sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
+ sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
+
+ interface = PCI_INTERFACE(pa->pa_class);
+ interface &= ~PCIIDE_CHANSTATUS_EN; /* Reserved on PC87415 */
+
+ /* If we're in PCIIDE mode, unmask INTA, otherwise mask it. */
+ ctl = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1);
+ if (interface & (PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1)))
+ ctl &= ~NATSEMI_CTRL1_INTAMASK;
+ else
+ ctl |= NATSEMI_CTRL1_INTAMASK;
+ pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1, ctl);
+
+ wdc_allocate_regs(&sc->sc_wdcdev);
+
+ for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; channel++) {
+ cp = &sc->pciide_channels[channel];
+ if (pciide_chansetup(sc, channel, interface) == 0)
+ continue;
+
+ pciide_mapchan(pa, cp, interface, natsemi_pci_intr);
+
+ pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2,
+ pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) &
+ ~(NATSEMI_CHMASK(channel)));
+ }
+}
+
+void
+natsemi_setup_channel(struct ata_channel *chp)
+{
+ struct ata_drive_datas *drvp;
+ int drive, ndrives = 0;
+ uint32_t idedma_ctl = 0;
+ struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
+ struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
+ uint8_t tim;
+
+ /* setup DMA if needed */
+ pciide_channel_dma_setup(cp);
+
+ for (drive = 0; drive < 2; drive++) {
+ drvp = &chp->ch_drive[drive];
+ /* If no drive, skip */
+ if ((drvp->drive_flags & DRIVE) == 0)
+ continue;
+
+ ndrives++;
+ /* add timing values, setup DMA if needed */
+ if ((drvp->drive_flags & DRIVE_DMA) == 0) {
+ tim = natsemi_pio_pulse[drvp->PIO_mode] |
+ (natsemi_pio_recover[drvp->PIO_mode] << 4);
+ } else {
+ /*
+ * use Multiword DMA
+ * Timings will be used for both PIO and DMA,
+ * so adjust DMA mode if needed
+ */
+ if (drvp->PIO_mode >= 3 &&
+ (drvp->DMA_mode + 2) > drvp->PIO_mode) {
+ drvp->DMA_mode = drvp->PIO_mode - 2;
+ }
+ idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
+ tim = natsemi_dma_pulse[drvp->DMA_mode] |
+ (natsemi_dma_recover[drvp->DMA_mode] << 4);
+
+ }
+
+ pciide_pci_write(sc->sc_pc, sc->sc_tag,
+ NATSEMI_RTREG(chp->ch_channel, drive), tim);
+ pciide_pci_write(sc->sc_pc, sc->sc_tag,
+ NATSEMI_WTREG(chp->ch_channel, drive), tim);
+ }
+
+ if (idedma_ctl != 0) {
+ /* Add software bits in status register */
+ bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
+ idedma_ctl);
+
+ }
+ /* Go ahead and ack interrupts generated during probe. */
+ natsemi_irqack(chp);
+}
+
+void
+natsemi_irqack(struct ata_channel *chp)
+{
+ struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
+ struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
+ uint8_t clr;
+
+ /* Errata: The "clear" bits are in the wrong register *sigh* */
+ clr = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0);
+ clr |= bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0) &
+ (IDEDMA_CTL_ERR | IDEDMA_CTL_INTR);
+ bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, clr);
+}
+
+int
+natsemi_pci_intr(void *arg)
+{
+ struct pciide_softc *sc = arg;
+ struct pciide_channel *cp;
+ struct ata_channel *wdc_cp;
+ int i, rv, crv;
+ uint8_t msk;
+
+ rv = 0;
+ msk = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2);
+ for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
+ cp = &sc->pciide_channels[i];
+ wdc_cp = &cp->ata_channel;
+
+ /* If a compat channel skip. */
+ if (cp->compat)
+ continue;
+
+ /* If this channel is masked, skip it. */
+ if (msk & NATSEMI_CHMASK(i))
+ continue;
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