[src/trunk]: src/sys/arch/arm/include fix XP bit and U bit definitions of CP1...

[bsh <bsh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/7cfb5c043424
branches:  trunk
changeset: 759726:7cfb5c043424
user:      bsh <bsh%NetBSD.org@localhost>
date:      Wed Dec 15 15:43:13 2010 +0000

description:
fix XP bit and U bit definitions of CP15 control register.
These constants are not used in our source tree for now,
so this won't change any kernel bianries.

diffstat:

 sys/arch/arm/include/armreg.h |  6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diffs (21 lines):

diff -r aae5f08572f0 -r 7cfb5c043424 sys/arch/arm/include/armreg.h
--- a/sys/arch/arm/include/armreg.h     Wed Dec 15 15:36:15 2010 +0000
+++ b/sys/arch/arm/include/armreg.h     Wed Dec 15 15:43:13 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armreg.h,v 1.45 2010/10/02 05:37:58 kiyohara Exp $     */
+/*     $NetBSD: armreg.h,v 1.46 2010/12/15 15:43:13 bsh Exp $  */
 
 /*
  * Copyright (c) 1998, 2001 Ben Harris
@@ -296,9 +296,9 @@
 #define CPU_CONTROL_VECRELOC   0x00002000 /* V: Vector relocation */
 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
 #define CPU_CONTROL_V4COMPAT   0x00008000 /* L4: ARMv4 compat LDR R15 etc */
-#define CPU_CONTROL_UNAL_ENABLE        0x00040000 /* U: unaligned data access */
-#define CPU_CONTROL_XP_ENABLE  0x00080000 /* XP: extended page table */
 #define CPU_CONTROL_FI_ENABLE  0x00200000 /* FI: Low interrupt latency */
+#define CPU_CONTROL_UNAL_ENABLE        0x00400000 /* U: unaligned data access */
+#define CPU_CONTROL_XP_ENABLE  0x00800000 /* XP: extended page table */
 
 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE