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[src/trunk]: src/sys/dev/pci Fix the bug that unaligned access occurs on amd6...
details: https://anonhg.NetBSD.org/src/rev/5adc79f39809
branches: trunk
changeset: 751337:5adc79f39809
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Mon Feb 01 05:38:36 2010 +0000
description:
Fix the bug that unaligned access occurs on amd64. It also fixes the bug
that error bits aren't cleard because these bits are W2C (in other word, W1C).
Reported by Michael van Elst.
diffstat:
sys/dev/pci/if_bge.c | 9 +++++----
sys/dev/pci/pcireg.h | 7 +++++--
2 files changed, 10 insertions(+), 6 deletions(-)
diffs (53 lines):
diff -r 8afea0cb15f0 -r 5adc79f39809 sys/dev/pci/if_bge.c
--- a/sys/dev/pci/if_bge.c Mon Feb 01 05:00:59 2010 +0000
+++ b/sys/dev/pci/if_bge.c Mon Feb 01 05:38:36 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_bge.c,v 1.178 2010/01/28 07:34:12 msaitoh Exp $ */
+/* $NetBSD: if_bge.c,v 1.179 2010/02/01 05:38:36 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
@@ -79,7 +79,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.178 2010/01/28 07:34:12 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.179 2010/02/01 05:38:36 msaitoh Exp $");
#include "vlan.h"
#include "rnd.h"
@@ -3113,10 +3113,11 @@
devctl &= ~(0x0010 | PCI_PCIE_DCSR_ENA_NO_SNOOP);
/* Set PCIE max payload size to 128. */
devctl &= ~(0x00e0);
+ /* Clear device status register. Write 1b to clear */
+ devctl |= PCI_PCIE_DCSR_URD | PCI_PCIE_DCSR_FED
+ | PCI_PCIE_DCSR_NFED | PCI_PCIE_DCSR_CED;
pci_conf_write(sc->sc_pc, sc->sc_pcitag,
sc->bge_expcap + PCI_PCIE_DCSR, devctl);
- pci_conf_write(sc->sc_pc, sc->sc_pcitag,
- sc->bge_expcap + PCI_PCIE_DSR, 0);
}
/* Reset some of the PCI state that got zapped by reset */
diff -r 8afea0cb15f0 -r 5adc79f39809 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h Mon Feb 01 05:00:59 2010 +0000
+++ b/sys/dev/pci/pcireg.h Mon Feb 01 05:38:36 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.62 2010/01/28 02:55:31 msaitoh Exp $ */
+/* $NetBSD: pcireg.h,v 1.63 2010/02/01 05:38:36 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -553,7 +553,10 @@
#define PCI_PCIE_DCSR 0x08
#define PCI_PCIE_DCSR_MAX_READ_REQ 0x7000
#define PCI_PCIE_DCSR_ENA_NO_SNOOP 0x00000800
-#define PCI_PCIE_DSR 0x0a
+#define PCI_PCIE_DCSR_CED 0x00010000
+#define PCI_PCIE_DCSR_NFED 0x00020000
+#define PCI_PCIE_DCSR_FED 0x00040000
+#define PCI_PCIE_DCSR_URD 0x00080000
#define PCI_PCIE_LCAP 0x0c
#define PCI_PCIE_LCSR 0x10
#define PCI_PCIE_LCSR_ASPM_L0S 0x00000001
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