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[src/netbsd-6]: src Pullup
details: https://anonhg.NetBSD.org/src/rev/48b1c58dd656
branches: netbsd-6
changeset: 776413:48b1c58dd656
user: martin <martin%NetBSD.org@localhost>
date: Mon Aug 05 10:09:53 2013 +0000
description:
Pullup
sys/dev/pci/pcireg.h 1.74-1.82 and 1.84 via patch
sys/dev/pci/pci_subr.c 1.92-1.102, 1.104-1.105 via patch
Add some PCI(e) register and bit definitions in pcireg.h.
Fix the definition of PCI_PCIE_SLCAP_PSN.
Fix a bug that IRQ(MSI) bits in PCIe capability register is incorrectly
decoded.
Print more registers in "pcictl dump".
Fix bug in comment.
Requested by msaitoh in ticket #928
diffstat:
doc/CHANGES-6.2 | 14 +-
sys/dev/pci/pci_subr.c | 573 +++++++++++++++++++++++++++++++++++++++++++++---
sys/dev/pci/pcireg.h | 150 +++++++++++-
3 files changed, 676 insertions(+), 61 deletions(-)
diffs (truncated from 911 to 300 lines):
diff -r 5d03394d5b43 -r 48b1c58dd656 doc/CHANGES-6.2
--- a/doc/CHANGES-6.2 Fri Aug 02 20:12:30 2013 +0000
+++ b/doc/CHANGES-6.2 Mon Aug 05 10:09:53 2013 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: CHANGES-6.2,v 1.1.2.28 2013/08/02 20:12:30 martin Exp $
+# $NetBSD: CHANGES-6.2,v 1.1.2.29 2013/08/05 10:09:53 martin Exp $
A complete list of changes from the 6.1 release until the 6.2 release:
@@ -456,3 +456,15 @@
Fix an inversion in checking for authorization to drop TCP connections
found (and the obvious fix suggested) by Sander Bos.
[spz, ticket #927]
+
+sys/dev/pci/pcireg.h 1.74-1.82 and 1.84 via patch
+sys/dev/pci/pci_subr.c 1.92-1.102, 1.104-1.105 via patch
+
+ Add some PCI(e) register and bit definitions in pcireg.h.
+ Fix the definition of PCI_PCIE_SLCAP_PSN.
+ Fix a bug that IRQ(MSI) bits in PCIe capability register is incorrectly
+ decoded.
+ Print more registers in "pcictl dump".
+ Fix bug in comment.
+ [msaitoh, ticket #928]
+
diff -r 5d03394d5b43 -r 48b1c58dd656 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c Fri Aug 02 20:12:30 2013 +0000
+++ b/sys/dev/pci/pci_subr.c Mon Aug 05 10:09:53 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.90 2012/01/29 11:31:38 drochner Exp $ */
+/* $NetBSD: pci_subr.c,v 1.90.2.1 2013/08/05 10:09:53 martin Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.90 2012/01/29 11:31:38 drochner Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.90.2.1 2013/08/05 10:09:53 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -90,6 +90,7 @@
{ "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, },
{ "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, },
{ "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, },
+ { "NVM", PCI_SUBCLASS_MASS_STORAGE_NVM, NULL, },
{ "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -118,6 +119,7 @@
{ "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, },
{ "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, },
{ "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
+ { "HD audio", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
{ "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -452,7 +454,7 @@
* in a device attach routine like this:
*
* #ifdef MYDEV_DEBUG
- * printf("%s: ", device_xname(&sc->sc_dev));
+ * printf("%s: ", device_xname(sc->sc_dev));
* pci_conf_print(pa->pa_pc, pa->pa_tag, NULL);
* #endif
*/
@@ -807,24 +809,112 @@
}
static void
+pci_print_pcie_L0s_latency(uint32_t val)
+{
+
+ switch (val) {
+ case 0x0:
+ printf("Less than 64ns\n");
+ break;
+ case 0x1:
+ case 0x2:
+ case 0x3:
+ printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1));
+ break;
+ case 0x4:
+ printf("512ns to less than 1us\n");
+ break;
+ case 0x5:
+ printf("1us to less than 2us\n");
+ break;
+ case 0x6:
+ printf("2us - 4us\n");
+ break;
+ case 0x7:
+ printf("More than 4us\n");
+ break;
+ }
+}
+
+static void
+pci_print_pcie_L1_latency(uint32_t val)
+{
+
+ switch (val) {
+ case 0x0:
+ printf("Less than 1us\n");
+ break;
+ case 0x6:
+ printf("32us - 64us\n");
+ break;
+ case 0x7:
+ printf("More than 64us\n");
+ break;
+ default:
+ printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val);
+ break;
+ }
+}
+
+static void
+pci_print_pcie_compl_timeout(uint32_t val)
+{
+
+ switch (val) {
+ case 0x0:
+ printf("50us to 50ms\n");
+ break;
+ case 0x5:
+ printf("16ms to 55ms\n");
+ break;
+ case 0x6:
+ printf("65ms to 210ms\n");
+ break;
+ case 0x9:
+ printf("260ms to 900ms\n");
+ break;
+ case 0xa:
+ printf("1s to 3.5s\n");
+ break;
+ default:
+ printf("unknown %u value\n", val);
+ break;
+ }
+}
+
+static void
pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
{
+ pcireg_t reg; /* for each register */
+ pcireg_t val; /* for each bitfield */
+ bool check_link = false;
bool check_slot = false;
+ bool check_rootport = false;
+ unsigned int pciever;
+ static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"};
+ int i;
printf("\n PCI Express Capabilities Register\n");
- printf(" Capability version: %x\n",
- (unsigned int)((regs[o2i(capoff)] & 0x000f0000) >> 16));
- printf(" Device type: ");
- switch ((regs[o2i(capoff)] & 0x00f00000) >> 20) {
+ /* Capability Register */
+ reg = regs[o2i(capoff)];
+ printf(" Capability register: %04x\n", reg >> 16);
+ pciever = (unsigned int)((reg & 0x000f0000) >> 16);
+ printf(" Capability version: %u\n", pciever);
+ printf(" Device type: ");
+ switch ((reg & 0x00f00000) >> 20) {
case 0x0:
printf("PCI Express Endpoint device\n");
+ check_link = true;
break;
case 0x1:
printf("Legacy PCI Express Endpoint device\n");
+ check_link = true;
break;
case 0x4:
printf("Root Port of PCI Express Root Complex\n");
+ check_link = true;
check_slot = true;
+ check_rootport = true;
break;
case 0x5:
printf("Upstream Port of PCI Express Switch\n");
@@ -832,6 +922,7 @@
case 0x6:
printf("Downstream Port of PCI Express Switch\n");
check_slot = true;
+ check_rootport = true;
break;
case 0x7:
printf("PCI Express to PCI/PCI-X Bridge\n");
@@ -839,53 +930,249 @@
case 0x8:
printf("PCI/PCI-X to PCI Express Bridge\n");
break;
+ case 0x9:
+ printf("Root Complex Integrated Endpoint\n");
+ break;
+ case 0xa:
+ check_rootport = true;
+ printf("Root Complex Event Collector\n");
+ break;
default:
printf("unknown\n");
break;
}
- if (check_slot && (regs[o2i(capoff)] & 0x01000000) != 0)
- printf(" Slot implemented\n");
- printf(" Interrupt Message Number: %x\n",
- (unsigned int)((regs[o2i(capoff)] & 0x4e000000) >> 27));
- printf(" Link Capabilities Register: 0x%08x\n",
- regs[o2i(capoff + 0x0c)]);
- printf(" Maximum Link Speed: ");
- if ((regs[o2i(capoff + 0x0c)] & 0x000f) != 1) {
- printf("unknown %u value\n",
- (regs[o2i(capoff + 0x0c)] & 0x000f));
- } else {
- printf("2.5Gb/s\n");
+ if (check_slot && (reg & PCI_PCIE_XCAP_SI) != 0)
+ printf(" Slot implemented\n");
+ printf(" Interrupt Message Number: %x\n",
+ (unsigned int)((reg & PCI_PCIE_XCAP_IRQ) >> 27));
+
+ /* Device Capability Register */
+ reg = regs[o2i(capoff + PCI_PCIE_DCAP)];
+ printf(" Device Capabilities Register: 0x%08x\n", reg);
+ printf(" Max Payload Size Supported: %u bytes max\n",
+ (unsigned int)(reg & PCI_PCIE_DCAP_MAX_PAYLOAD) * 256);
+ printf(" Phantom Functions Supported: ");
+ switch ((reg & PCI_PCIE_DCAP_PHANTOM_FUNCS) >> 3) {
+ case 0x0:
+ printf("not available\n");
+ break;
+ case 0x1:
+ printf("MSB\n");
+ break;
+ case 0x2:
+ printf("two MSB\n");
+ break;
+ case 0x3:
+ printf("All three bits\n");
+ break;
}
- printf(" Maximum Link Width: x%u lanes\n",
- (regs[o2i(capoff + 0x0c)] & 0x03f0) >> 4);
- printf(" Port Number: %u\n", regs[o2i(capoff + 0x0c)] >> 24);
- printf(" Link Status Register: 0x%04x\n",
- regs[o2i(capoff + 0x10)] >> 16);
- printf(" Negotiated Link Speed: ");
- if (((regs[o2i(capoff + 0x10)] >> 16) & 0x000f) != 1) {
- printf("unknown %u value\n",
- (regs[o2i(capoff + 0x10)] >> 16) & 0x000f);
- } else {
- printf("2.5Gb/s\n");
+ printf(" Extended Tag Field Supported: %dbit\n",
+ (reg & PCI_PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8);
+ printf(" Endpoint L0 Acceptable Latency: ");
+ pci_print_pcie_L0s_latency((reg & PCI_PCIE_DCAP_L0S_LATENCY) >> 6);
+ printf(" Endpoint L1 Acceptable Latency: ");
+ pci_print_pcie_L1_latency((reg & PCI_PCIE_DCAP_L1_LATENCY) >> 9);
+ printf(" Attention Button Present: %s\n",
+ (reg & PCI_PCIE_DCAP_ATTN_BUTTON) != 0 ? "yes" : "no");
+ printf(" Attention Indicator Present: %s\n",
+ (reg & PCI_PCIE_DCAP_ATTN_IND) != 0 ? "yes" : "no");
+ printf(" Power Indicator Present: %s\n",
+ (reg & PCI_PCIE_DCAP_PWR_IND) != 0 ? "yes" : "no");
+ printf(" Role-Based Error Report: %s\n",
+ (reg & PCI_PCIE_DCAP_ROLE_ERR_RPT) != 0 ? "yes" : "no");
+ printf(" Captured Slot Power Limit Value: %d\n",
+ (unsigned int)(reg & PCI_PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18);
+ printf(" Captured Slot Power Limit Scale: %d\n",
+ (unsigned int)(reg & PCI_PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26);
+ printf(" Function-Level Reset Capability: %s\n",
+ (reg & PCI_PCIE_DCAP_FLR) != 0 ? "yes" : "no");
+
+ /* Device Control Register */
+ reg = regs[o2i(capoff + PCI_PCIE_DCSR)];
+ printf(" Device Control Register: 0x%04x\n", reg & 0xffff);
+ printf(" Correctable Error Reporting Enable: %s\n",
+ (reg & PCI_PCIE_DCSR_ENA_COR_ERR) != 0 ? "on" : "off");
+ printf(" Non Fatal Error Reporting Enable: %s\n",
+ (reg & PCI_PCIE_DCSR_ENA_NFER) != 0 ? "on" : "off");
+ printf(" Fatal Error Reporting Enable: %s\n",
+ (reg & PCI_PCIE_DCSR_ENA_FER) != 0 ? "on" : "off");
+ printf(" Unsupported Request Reporting Enable: %s\n",
+ (reg & PCI_PCIE_DCSR_ENA_URR) != 0 ? "on" : "off");
+ printf(" Enable Relaxed Ordering: %s\n",
+ (reg & PCI_PCIE_DCSR_ENA_RELAX_ORD) != 0 ? "on" : "off");
+ printf(" Max Payload Size: %d byte\n",
+ 128 << (((unsigned int)(reg & PCI_PCIE_DCSR_MAX_PAYLOAD) >> 5)));
+ printf(" Extended Tag Field Enable: %s\n",
+ (reg & PCI_PCIE_DCSR_EXT_TAG_FIELD) != 0 ? "on" : "off");
+ printf(" Phantom Functions Enable: %s\n",
+ (reg & PCI_PCIE_DCSR_PHANTOM_FUNCS) != 0 ? "on" : "off");
+ printf(" Aux Power PM Enable: %s\n",
+ (reg & PCI_PCIE_DCSR_AUX_POWER_PM) != 0 ? "on" : "off");
+ printf(" Enable No Snoop: %s\n",
+ (reg & PCI_PCIE_DCSR_ENA_NO_SNOOP) != 0 ? "on" : "off");
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