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[src/trunk]: src/sys/arch/powerpc/include Split <powerpc/spr.h> into a common...
details: https://anonhg.NetBSD.org/src/rev/65cf2052c228
branches: trunk
changeset: 752434:65cf2052c228
user: matt <matt%NetBSD.org@localhost>
date: Thu Feb 25 23:30:04 2010 +0000
description:
Split <powerpc/spr.h> into a common <powerpc/spr.h> and <powerpc/XXX/spr.h>
where XXX is ibm4xx or oea.
diffstat:
sys/arch/powerpc/include/ibm4xx/Makefile | 4 +-
sys/arch/powerpc/include/ibm4xx/spr.h | 151 ++++++++
sys/arch/powerpc/include/oea/Makefile | 4 +-
sys/arch/powerpc/include/oea/spr.h | 288 ++++++++++++++++
sys/arch/powerpc/include/spr.h | 539 +-----------------------------
5 files changed, 466 insertions(+), 520 deletions(-)
diffs (truncated from 1033 to 300 lines):
diff -r 44e9a5725613 -r 65cf2052c228 sys/arch/powerpc/include/ibm4xx/Makefile
--- a/sys/arch/powerpc/include/ibm4xx/Makefile Thu Feb 25 23:10:49 2010 +0000
+++ b/sys/arch/powerpc/include/ibm4xx/Makefile Thu Feb 25 23:30:04 2010 +0000
@@ -1,7 +1,7 @@
-# $NetBSD: Makefile,v 1.5 2005/12/11 12:18:43 christos Exp $
+# $NetBSD: Makefile,v 1.6 2010/02/25 23:30:05 matt Exp $
INCSDIR= /usr/include/powerpc/ibm4xx
-INCS= cpu.h pmap.h tlb.h
+INCS= cpu.h pmap.h spr.h tlb.h
.include <bsd.kinc.mk>
diff -r 44e9a5725613 -r 65cf2052c228 sys/arch/powerpc/include/ibm4xx/spr.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/powerpc/include/ibm4xx/spr.h Thu Feb 25 23:30:04 2010 +0000
@@ -0,0 +1,151 @@
+/* $NetBSD: spr.h,v 1.1 2010/02/25 23:30:05 matt Exp $ */
+
+#ifndef _POWERPC_IBM4XX_SPR_H_
+#define _POWERPC_IBM4XX_SPR_H_
+
+/*
+ * IBM4xx Special Purpose Register declarations.
+ *
+ * The first column in the comments indicates which PowerPC architectures the
+ * SPR is valid on - E for BookE series, 4 for 4xx series,
+ * 6 for 6xx/7xx series and 8 for 8xx and 8xxx (but not 85xx) series.
+ */
+
+#define SPR_44XPID 0x030 /* E4.. 440 Process ID */
+#define SPR_USPRG0 0x100 /* E4.. User SPR General 0 */
+#define IBM403 0x0020
+#define IBM401A1 0x0021
+#define IBM401B2 0x0022
+#define IBM401C2 0x0023
+#define IBM401D2 0x0024
+#define IBM401E2 0x0025
+#define IBM401F2 0x0026
+#define IBM401G2 0x0027
+#define XILVIRTEX 0x2001
+#define IBM405GP 0x4011
+#define IBMSTB03 0x4013
+#define IBMSTB04 0x4081
+#define IBM405GS3 0x40b1
+#define IBM405H 0x4141
+#define IBM405L 0x4161
+#define IBM405LP 0x41f1
+#define IBM405GPR 0x5091
+#define IBM405EP 0x5121
+#define IBMSTB25 0x5151
+
+#define SPR_ZPR 0x3b0 /* .4.. Zone Protection Register */
+#define SPR_PID 0x3b1 /* .4.. Process ID */
+#define SPR_MMUCR 0x3b2 /* .4.. MMU Control Register */
+#define MMUCR_SW0A 0x01000000 /* Store WithOut Allocate */
+#define MMUCR_U1TE 0x00400000 /* U1 Transient Enable */
+#define MMUCR_U2SWOAE 0x00200000 /* U2 SWOA Enab */
+#define MMUCR_DULXE 0x00080000 /* Data Cache Unlock Exc. Ena. */
+#define MMUCR_IULXE 0x00040000 /* Inst. Cache Unlock Exc. Ena. */
+#define MMUCR_STS 0x00010000 /* Search Translation Space [TS] */
+#define MMUCR_STID 0x000000ff /* Search Translation ID */
+#define SPR_CCR0 0x3b3 /* .4.. Core Configuration Register 0 */
+#define SPR_IAC3 0x3b4 /* .4.. Instruction Address Compare 3 */
+#define SPR_IAC4 0x3b5 /* .4.. Instruction Address Compare 4 */
+#define SPR_DVC1 0x3b6 /* .4.. Data Value Compare 1 */
+#define SPR_DVC2 0x3b7 /* .4.. Data Value Compare 2 */
+#define SPR_SGR 0x3b9 /* .4.. Storage Guarded Register */
+#define SPR_DCWR 0x3ba /* .4.. Data Cache Write-through Register */
+#define SPR_SLER 0x3bb /* .4.. Storage Little Endian Register */
+#define SPR_SU0R 0x3bc /* .4.. Storage User-defined 0 Register */
+#define SPR_DBCR1 0x3bd /* .4.. Debug Control Register 1 */
+#define SPR_ICDBDR 0x3d3 /* .4.. Instruction Cache Debug Data Register */
+#define SPR_ESR 0x3d4 /* .4.. Exception Syndrome Register */
+#define ESR_MCI 0x80000000 /* 0: Machine check - instruction */
+#define ESR_PIL 0x08000000 /* 4: Program interrupt - illegal */
+#define ESR_PPR 0x04000000 /* 5: Program interrupt - privileged */
+#define ESR_PTR 0x02000000 /* 6: Program interrupt - trap */
+#define ESR_DST 0x00800000 /* 8: Data storage interrupt - store fault */
+#define ESR_DIZ 0x00800000 /* 8: Data/instruction storage interrupt - zone fault */
+#define ESR_ST 0x00800000 /* 8: Store operation */
+#define ESR_DLK 0x00200000 /* 10: dcache exception */
+#define ESR_ILK 0x00100000 /* 11: icache exception */
+#define ESR_BO 0x00020000 /* 14: Byte ordering exception */
+#define ESR_U0F 0x00008000 /* 16: Data storage interrupt - U0 fault */
+#define ESR_SPE 0x00000080 /* 24: SPE exception */
+#define SPR_DEAR 0x3d5 /* .4.. Data Error Address Register */
+#define SPR_EVPR 0x3d6 /* .4.. Exception Vector Prefix Register */
+#define SPR_TSR 0x3d8 /* .4.. Timer Status Register */
+#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
+#define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */
+#define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */
+#define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */
+#define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */
+#define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */
+#define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */
+#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
+#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
+#define SPR_TCR 0x3da /* .4.. Timer Control Register */
+#define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */
+#define TCR_WP_2_17 0x00000000 /* 2**17 clocks */
+#define TCR_WP_2_21 0x40000000 /* 2**21 clocks */
+#define TCR_WP_2_25 0x80000000 /* 2**25 clocks */
+#define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */
+#define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */
+#define TCR_WRC_NONE 0x00000000 /* No watchdog reset */
+#define TCR_WRC_CORE 0x10000000 /* Core reset */
+#define TCR_WRC_CHIP 0x20000000 /* Chip reset */
+#define TCR_WRC_SYSTEM 0x30000000 /* System reset */
+#define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */
+#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
+#define TCR_FP_MASK 0x03000000 /* FIT Period */
+#define TCR_FP_2_9 0x00000000 /* 2**9 clocks */
+#define TCR_FP_2_13 0x01000000 /* 2**13 clocks */
+#define TCR_FP_2_17 0x02000000 /* 2**17 clocks */
+#define TCR_FP_2_21 0x03000000 /* 2**21 clocks */
+#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
+#define TCR_ARE 0x00400000 /* Auto Reload Enable */
+#define SPR_PIT 0x3db /* .4.. Programmable Interval Timer */
+#define SPR_SRR2 0x3de /* .4.. Save/Restore Register 2 */
+#define SPR_SRR3 0x3df /* .4.. Save/Restore Register 3 */
+#define SPR_DBSR 0x3f0 /* .4.. Debug Status Register */
+#define DBSR_IC 0x80000000 /* Instruction completion debug event */
+#define DBSR_IDE 0x80000000 /* Imprecise debug event */
+#define DBSR_BT 0x40000000 /* Branch Taken debug event */
+#define DBSR_EDE 0x20000000 /* Exception debug event */
+#define DBSR_TIE 0x10000000 /* Trap Instruction debug event */
+#define DBSR_UDE 0x08000000 /* Unconditional debug event */
+#define DBSR_IA1 0x04000000 /* IAC1 debug event */
+#define DBSR_IA2 0x02000000 /* IAC2 debug event */
+#define DBSR_DR1 0x01000000 /* DAC1 Read debug event */
+#define DBSR_DW1 0x00800000 /* DAC1 Write debug event */
+#define DBSR_DR2 0x00400000 /* DAC2 Read debug event */
+#define DBSR_DW2 0x00200000 /* DAC2 Write debug event */
+#define DBSR_IA3 0x00080000 /* IAC3 debug event */
+#define DBSR_IA4 0x00040000 /* IAC4 debug event */
+#define DBSR_MRR 0x00000300 /* Most recent reset */
+#define SPR_DBCR0 0x3f2 /* .4.. Debug Control Register 0 */
+#define DBCR0_EDM 0x80000000 /* 0: External Debug Mode */
+#define DBCR0_IDM 0x40000000 /* 1: Internal Debug Mode */
+#define DBCR0_RST_MASK 0x30000000 /* 2..3: ReSeT */
+#define DBCR0_RST_NONE 0x00000000 /* No action */
+#define DBCR0_RST_CORE 0x10000000 /* Core reset */
+#define DBCR0_RST_CHIP 0x20000000 /* Chip reset */
+#define DBCR0_RST_SYSTEM 0x30000000 /* System reset */
+#define DBCR0_IC 0x08000000 /* 4: Instruction Completion debug event */
+#define DBCR0_BT 0x04000000 /* 5: Branch Taken debug event */
+#define DBCR0_EDE 0x02000000 /* 6: Exception Debug Event */
+#define DBCR0_TDE 0x01000000 /* 7: Trap Debug Event */
+#define DBCR0_IA1 0x00800000 /* 8: IAC (Instruction Address Compare) 1 debug event */
+#define DBCR0_IA2 0x00400000 /* 9: IAC 2 debug event */
+#define DBCR0_IA12 0x00200000 /* 10: Instruction Address Range Compare 1-2 */
+#define DBCR0_IA12X 0x00100000 /* 11: IA12 eXclusive */
+#define DBCR0_IA3 0x00080000 /* 12: IAC 3 debug event */
+#define DBCR0_IA4 0x00040000 /* 13: IAC 4 debug event */
+#define DBCR0_IA34 0x00020000 /* 14: Instruction Address Range Compare 3-4 */
+#define DBCR0_IA34X 0x00010000 /* 15: IA34 eXclusive */
+#define DBCR0_IA12T 0x00008000 /* 16: Instruction Address Range Compare 1-2 range Toggle */
+#define DBCR0_IA34T 0x00004000 /* 17: Instruction Address Range Compare 3-4 range Toggle */
+#define DBCR0_FT 0x00000001 /* 31: Freeze Timers on debug event */
+#define SPR_IAC1 0x3f4 /* .4.. Instruction Address Compare 1 */
+#define SPR_IAC2 0x3f5 /* .4.. Instruction Address Compare 2 */
+#define SPR_DAC1 0x3f6 /* .4.. Data Address Compare 1 */
+#define SPR_DAC2 0x3f7 /* .4.. Data Address Compare 2 */
+#define SPR_DCCR 0x3fa /* .4.. Data Cache Cachability Register */
+#define SPR_ICCR 0x3fb /* .4.. Instruction Cache Cachability Register */
+
+#endif /* !_POWERPC_IBM4XX_SPR_H_ */
diff -r 44e9a5725613 -r 65cf2052c228 sys/arch/powerpc/include/oea/Makefile
--- a/sys/arch/powerpc/include/oea/Makefile Thu Feb 25 23:10:49 2010 +0000
+++ b/sys/arch/powerpc/include/oea/Makefile Thu Feb 25 23:30:04 2010 +0000
@@ -1,11 +1,11 @@
-# $NetBSD: Makefile,v 1.1 2003/02/03 17:10:05 matt Exp $
+# $NetBSD: Makefile,v 1.2 2010/02/25 23:30:05 matt Exp $
INCSDIR= /usr/include/powerpc/oea
INCS= bat.h \
hid.h hid_601.h \
pmap.h pte.h \
- sr_601.h \
+ spr.h sr_601.h \
vmparam.h
.include <bsd.kinc.mk>
diff -r 44e9a5725613 -r 65cf2052c228 sys/arch/powerpc/include/oea/spr.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/powerpc/include/oea/spr.h Thu Feb 25 23:30:04 2010 +0000
@@ -0,0 +1,288 @@
+/* $NetBSD: spr.h,v 1.1 2010/02/25 23:30:05 matt Exp $ */
+
+#ifndef _POWERPC_OEA_SPR_H_
+#define _POWERPC_OEA_SPR_H_
+
+/*
+ * Special Purpose Register declarations.
+ *
+ * The first column in the comments indicates which PowerPC architectures the
+ * SPR is valid on - E for BookE series, 4 for 4xx series,
+ * 6 for 6xx/7xx series and 8 for 8xx (but not most 8xxx) series.
+ */
+
+#define SPR_MQ 0x000 /* ..6. 601 MQ register */
+#define SPR_RTCU_R 0x004 /* ..6. 601 RTC Upper - Read */
+#define SPR_RTCL_R 0x005 /* ..6. 601 RTC Lower - Read */
+#define SPR_DSISR 0x012 /* ..68 DSI exception source */
+#define DSISR_DIRECT 0x80000000 /* Direct-store error exception */
+#define DSISR_NOTFOUND 0x40000000 /* Translation not found */
+#define DSISR_PROTECT 0x08000000 /* Memory access not permitted */
+#define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */
+#define DSISR_STORE 0x02000000 /* Store operation */
+#define DSISR_DABR 0x00400000 /* DABR match */
+#define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */
+#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */
+#define SPR_DAR 0x013 /* ..68 Data Address Register */
+#define SPR_RTCU_W 0x014 /* ..6. 601 RTC Upper - Write */
+#define SPR_RTCL_W 0x015 /* ..6. 601 RTC Lower - Write */
+#define SPR_SDR1 0x019 /* ..68 Page table base address register */
+#define SPR_VRSAVE 0x100 /* ..6. AltiVec VRSAVE */
+#define SPR_ASR 0x118 /* ..6. Address Space Register (PPC64) */
+#define SPR_EAR 0x11a /* ..68 External Access Register */
+#define MPC601 0x0001
+#define MPC603 0x0003
+#define MPC604 0x0004
+#define MPC602 0x0005
+#define MPC603e 0x0006
+#define MPC603ev 0x0007
+#define MPC750 0x0008
+#define MPC604e 0x0009
+#define MPC604ev 0x000a
+#define MPC7400 0x000c
+#define MPC620 0x0014
+#define IBMRS64II 0x0033
+#define IBMRS64IIIp 0x0034
+#define IBMPOWER4 0x0035
+#define IBMRS64IIIi 0x0036
+#define IBMRS64IV 0x0037
+#define IBMPOWER4II 0x0038
+#define IBM970 0x0039
+#define IBMPOWER5GR 0x003a
+#define IBMPOWER5GS 0x003b
+#define IBM970FX 0x003c
+#define IBMPOWER6 0x003e
+#define IBMPOWER3 0x0040
+#define IBMPOWER3II 0x0041
+#define IBM970MP 0x0044
+#define IBM970GX 0x0045
+#define IBMCELL 0x0070
+#define MPC8240 0x0081
+#define PA6T 0x0090
+#define IBMPOWER6P5 0x0f00
+#define IBMSTB25 0x5151
+#define IBM750FX 0x7000
+#define IBM750GX 0x7002
+#define MPC7450 0x8000
+#define MPC7455 0x8001
+#define MPC7457 0x8002
+#define MPC7447A 0x8003
+#define MPC7448 0x8004
+#define MPC745X_P(v) ((v & 0xFFF8) == 0x8000)
+#define MPC7410 0x800c
+#define MPC5200 0x8011
+#define MPC8245 0x8081
+#define MPCG2 0x8082
+#define MPCe300c1 0x8083
+#define MPCe300c2 0x8084
+#define MPCe300c3 0x8085
+
+#define SPR_IBAT0U 0x210 /* ..68 Instruction BAT Reg 0 Upper */
+#define SPR_IBAT0L 0x211 /* ..6. Instruction BAT Reg 0 Lower */
+#define SPR_IBAT1U 0x212 /* ..6. Instruction BAT Reg 1 Upper */
+#define SPR_IBAT1L 0x213 /* ..6. Instruction BAT Reg 1 Lower */
+#define SPR_IBAT2U 0x214 /* ..6. Instruction BAT Reg 2 Upper */
+#define SPR_IBAT2L 0x215 /* ..6. Instruction BAT Reg 2 Lower */
+#define SPR_IBAT3U 0x216 /* ..6. Instruction BAT Reg 3 Upper */
+#define SPR_IBAT3L 0x217 /* ..6. Instruction BAT Reg 3 Lower */
+#define SPR_DBAT0U 0x218 /* ..6. Data BAT Reg 0 Upper */
+#define SPR_DBAT0L 0x219 /* ..6. Data BAT Reg 0 Lower */
+#define SPR_DBAT1U 0x21a /* ..6. Data BAT Reg 1 Upper */
+#define SPR_DBAT1L 0x21b /* ..6. Data BAT Reg 1 Lower */
+#define SPR_DBAT2U 0x21c /* ..6. Data BAT Reg 2 Upper */
+#define SPR_DBAT2L 0x21d /* ..6. Data BAT Reg 2 Lower */
+#define SPR_DBAT3U 0x21e /* ..6. Data BAT Reg 3 Upper */
+#define SPR_DBAT3L 0x21f /* ..6. Data BAT Reg 3 Lower */
+#define SPR_IBAT4U 0x230 /* ..6. Instruction BAT Reg 4 Upper */
+#define SPR_IBAT4L 0x231 /* ..6. Instruction BAT Reg 4 Lower */
+#define SPR_IBAT5U 0x232 /* ..6. Instruction BAT Reg 5 Upper */
+#define SPR_IBAT5L 0x233 /* ..6. Instruction BAT Reg 5 Lower */
+#define SPR_IBAT6U 0x234 /* ..6. Instruction BAT Reg 6 Upper */
+#define SPR_IBAT6L 0x235 /* ..6. Instruction BAT Reg 6 Lower */
+#define SPR_IBAT7U 0x236 /* ..6. Instruction BAT Reg 7 Upper */
+#define SPR_IBAT7L 0x237 /* ..6. Instruction BAT Reg 7 Lower */
+#define SPR_DBAT4U 0x238 /* ..6. Data BAT Reg 4 Upper */
+#define SPR_DBAT4L 0x239 /* ..6. Data BAT Reg 4 Lower */
+#define SPR_DBAT5U 0x23a /* ..6. Data BAT Reg 5 Upper */
+#define SPR_DBAT5L 0x23b /* ..6. Data BAT Reg 5 Lower */
+#define SPR_DBAT6U 0x23c /* ..6. Data BAT Reg 6 Upper */
+#define SPR_DBAT6L 0x23d /* ..6. Data BAT Reg 6 Lower */
+#define SPR_DBAT7U 0x23e /* ..6. Data BAT Reg 7 Upper */
+#define SPR_UMMCR2 0x3a0 /* ..6. User Monitor Mode Control Register 2 */
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