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[src/matt-nb6-plus]: src/sys Sync with HEAD
details: https://anonhg.NetBSD.org/src/rev/ed964d6a87d6
branches: matt-nb6-plus
changeset: 774554:ed964d6a87d6
user: matt <matt%NetBSD.org@localhost>
date: Wed Feb 13 23:52:02 2013 +0000
description:
Sync with HEAD
diffstat:
sys/arch/arm/arm32/pmap.c | 40 +++++++++++++++++++++++++++++++++-
sys/arch/arm/broadcom/bcm53xx_board.c | 26 ++++++++++++++--------
sys/arch/arm/include/bus_defs.h | 5 ++-
sys/sys/bus_proto.h | 4 ++-
4 files changed, 60 insertions(+), 15 deletions(-)
diffs (198 lines):
diff -r 9af927679169 -r ed964d6a87d6 sys/arch/arm/arm32/pmap.c
--- a/sys/arch/arm/arm32/pmap.c Fri Feb 08 02:22:41 2013 +0000
+++ b/sys/arch/arm/arm32/pmap.c Wed Feb 13 23:52:02 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.228.2.1.2.2 2013/02/07 06:52:53 matt Exp $ */
+/* $NetBSD: pmap.c,v 1.228.2.1.2.3 2013/02/13 23:52:02 matt Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@@ -212,7 +212,7 @@
#include <arm/cpuconf.h>
#include <arm/arm32/katelib.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.228.2.1.2.2 2013/02/07 06:52:53 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.228.2.1.2.3 2013/02/13 23:52:02 matt Exp $");
#ifdef PMAP_DEBUG
@@ -605,14 +605,32 @@
* Macro to determine if a mapping might be resident in the
* instruction cache and/or TLB
*/
+#if ARM_MMU_V7 > 0
+/*
+ * Speculative loads by Cortex cores can cause TLB entries to be filled even if
+ * there are no explicit accesses, so there may be always be TLB entries to
+ * flush. If we used ASIDs then this would not be a problem.
+ */
+#define PV_BEEN_EXECD(f) (((f) & PVF_EXEC) == PVF_EXEC)
+#else
#define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
+#endif
#define PV_IS_EXEC_P(f) (((f) & PVF_EXEC) != 0)
/*
* Macro to determine if a mapping might be resident in the
* data cache and/or TLB
*/
+#if ARM_MMU_V7 > 0
+/*
+ * Speculative loads by Cortex cores can cause TLB entries to be filled even if
+ * there are no explicit accesses, so there may be always be TLB entries to
+ * flush. If we used ASIDs then this would not be a problem.
+ */
+#define PV_BEEN_REFD(f) (1)
+#else
#define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
+#endif
/*
* Local prototypes
@@ -726,7 +744,16 @@
if (pm->pm_cstate.cs_tlb_id) {
cpu_tlb_flushID();
+#if ARM_MMU_V7 == 0
+ /*
+ * Speculative loads by Cortex cores can cause TLB entries to
+ * be filled even if there are no explicit accesses, so there
+ * may be always be TLB entries to flush. If we used ASIDs
+ * then it would not be a problem.
+ * This is not true for other CPUs.
+ */
pm->pm_cstate.cs_tlb = 0;
+#endif
}
}
@@ -736,7 +763,16 @@
if (pm->pm_cstate.cs_tlb_d) {
cpu_tlb_flushD();
+#if ARM_MMU_V7 == 0
+ /*
+ * Speculative loads by Cortex cores can cause TLB entries to
+ * be filled even if there are no explicit accesses, so there
+ * may be always be TLB entries to flush. If we used ASIDs
+ * then it would not be a problem.
+ * This is not true for other CPUs.
+ */
pm->pm_cstate.cs_tlb_d = 0;
+#endif
}
}
diff -r 9af927679169 -r ed964d6a87d6 sys/arch/arm/broadcom/bcm53xx_board.c
--- a/sys/arch/arm/broadcom/bcm53xx_board.c Fri Feb 08 02:22:41 2013 +0000
+++ b/sys/arch/arm/broadcom/bcm53xx_board.c Wed Feb 13 23:52:02 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm53xx_board.c,v 1.8.4.3 2013/02/07 06:51:48 matt Exp $ */
+/* $NetBSD: bcm53xx_board.c,v 1.8.4.4 2013/02/13 23:52:18 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.8.4.3 2013/02/07 06:51:48 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.8.4.4 2013/02/13 23:52:18 matt Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -66,7 +66,7 @@
static struct cpu_softc cpu_softc;
-struct arm32_dma_range bcm53xx_dma_ranges[2] = {
+struct arm32_dma_range bcm53xx_dma_ranges[] = {
[0] = {
.dr_sysbase = 0x80000000,
.dr_busbase = 0x80000000,
@@ -85,15 +85,17 @@
_BUS_DMATAG_FUNCS,
};
-struct arm32_dma_range bcm53xx_coherent_dma_ranges[2] = {
+struct arm32_dma_range bcm53xx_coherent_dma_ranges[] = {
[0] = {
.dr_sysbase = 0x80000000,
.dr_busbase = 0x80000000,
.dr_len = 0x10000000,
.dr_flags = _BUS_DMAMAP_COHERENT,
+#ifndef _ARM32_NEED_BUS_DMA_BOUNCE
}, [1] = {
.dr_sysbase = 0x90000000,
.dr_busbase = 0x90000000,
+#endif
},
};
@@ -521,19 +523,23 @@
void
bcm53xx_dma_bootstrap(psize_t memsize)
{
- if (memsize > 256*1024*1024) {
+ if (memsize <= 256*1024*1024) {
+ bcm53xx_dma_ranges[0].dr_len = memsize;
+ bcm53xx_coherent_dma_ranges[0].dr_len = memsize;
+ bcm53xx_dma_tag._nranges = 1;
+#ifndef _ARM32_NEED_BUS_DMA_BOUNCE
+ bcm53xx_coherent_dma_tag._nranges = 1;
+#endif
+ } else {
/*
* By setting up two ranges, bus_dmamem_alloc will always
* try to allocate from range 0 first resulting in allocations
* below 256MB which for PCI and GMAC are coherent.
*/
bcm53xx_dma_ranges[1].dr_len = memsize - 0x10000000;
+#ifndef _ARM32_NEED_BUS_DMA_BOUNCE
bcm53xx_coherent_dma_ranges[1].dr_len = memsize - 0x10000000;
- } else {
- bcm53xx_dma_ranges[0].dr_len = memsize;
- bcm53xx_coherent_dma_ranges[0].dr_len = memsize;
- bcm53xx_dma_tag._nranges = 1;
- bcm53xx_coherent_dma_tag._nranges = 1;
+#endif
}
KASSERT(bcm53xx_dma_tag._ranges[0].dr_flags == 0);
KASSERT(bcm53xx_coherent_dma_tag._ranges[0].dr_flags == _BUS_DMAMAP_COHERENT);
diff -r 9af927679169 -r ed964d6a87d6 sys/arch/arm/include/bus_defs.h
--- a/sys/arch/arm/include/bus_defs.h Fri Feb 08 02:22:41 2013 +0000
+++ b/sys/arch/arm/include/bus_defs.h Wed Feb 13 23:52:02 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_defs.h,v 1.1.10.1 2012/11/28 22:40:28 matt Exp $ */
+/* $NetBSD: bus_defs.h,v 1.1.10.2 2013/02/13 23:52:45 matt Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
@@ -300,7 +300,8 @@
* Private flags stored in the DMA map.
*/
#define _BUS_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */
-#define _BUS_DMAMAP_IS_BOUNCING 0x20000 /* is bouncing current xfer */
+#define _BUS_DMAMAP_IS_BOUNCING 0x20000 /* is bouncing current xfer */
+#define _BUS_DMAMAP_NOALLOC 0x40000 /* don't alloc memory from this range */
/* Forwards needed by prototypes below. */
struct mbuf;
diff -r 9af927679169 -r ed964d6a87d6 sys/sys/bus_proto.h
--- a/sys/sys/bus_proto.h Fri Feb 08 02:22:41 2013 +0000
+++ b/sys/sys/bus_proto.h Wed Feb 13 23:52:02 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_proto.h,v 1.6 2011/08/17 10:46:38 martin Exp $ */
+/* $NetBSD: bus_proto.h,v 1.6.10.1 2013/02/13 23:52:45 matt Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2001, 2007 The NetBSD Foundation, Inc.
@@ -319,6 +319,8 @@
#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */
+#define BUS_DMA_PREFETCHABLE 0x800 /* hint: map non-cached but allow
+ * things like write combining */
/* Operations performed by bus_dmamap_sync(). */
#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
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