[src/trunk]: src/sys/arch/landisk/landisk sync with OpenBSD:r1.3

[nonaka <nonaka%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/38d46b8df9ce
branches:  trunk
changeset: 753248:38d46b8df9ce
user:      nonaka <nonaka%NetBSD.org@localhost>
date:      Sun Mar 21 14:49:28 2010 +0000

description:
sync with OpenBSD:r1.3
> bus_dmamap_sync fixes to cope with real life.

diffstat:

 sys/arch/landisk/landisk/bus_dma.c |  25 ++++++++++++++++---------
 1 files changed, 16 insertions(+), 9 deletions(-)

diffs (54 lines):

diff -r 05bb6903e270 -r 38d46b8df9ce sys/arch/landisk/landisk/bus_dma.c
--- a/sys/arch/landisk/landisk/bus_dma.c        Sun Mar 21 14:29:04 2010 +0000
+++ b/sys/arch/landisk/landisk/bus_dma.c        Sun Mar 21 14:49:28 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: bus_dma.c,v 1.10 2010/03/21 13:34:19 nonaka Exp $      */
+/*     $NetBSD: bus_dma.c,v 1.11 2010/03/21 14:49:28 nonaka Exp $      */
 
 /*
  * Copyright (c) 2005 NONAKA Kimihiro
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.10 2010/03/21 13:34:19 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.11 2010/03/21 14:49:28 nonaka Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -527,21 +527,28 @@
 
                switch (ops) {
                case BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE:
-                       sh_dcache_wbinv_range(naddr, minlen);
+                       if (SH_HAS_WRITEBACK_CACHE)
+                               sh_dcache_wbinv_range(naddr, minlen);
+                       else
+                               sh_dcache_inv_range(naddr, minlen);
                        break;
 
                case BUS_DMASYNC_PREREAD:
-                       if (((naddr | minlen) & (~(sh_cache_line_size - 1))) == 0) {
+                       if (SH_HAS_WRITEBACK_CACHE &&
+                           ((naddr | minlen) & (sh_cache_line_size - 1)) != 0)
+                               sh_dcache_wbinv_range(naddr, minlen);
+                       else
                                sh_dcache_inv_range(naddr, minlen);
-                       } else {
-                               sh_dcache_wbinv_range(naddr, minlen);
-                       }
                        break;
 
                case BUS_DMASYNC_PREWRITE:
-                       if (SH_HAS_WRITEBACK_CACHE) {
+                       if (SH_HAS_WRITEBACK_CACHE)
                                sh_dcache_wb_range(naddr, minlen);
-                       }
+                       break;
+
+               case BUS_DMASYNC_POSTREAD:
+               case BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE:
+                       sh_dcache_inv_range(naddr, minlen);
                        break;
                }
                offset = 0;