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[src/trunk]: src/sys/arch/arm/imx Some initial iMX.6 support
details: https://anonhg.NetBSD.org/src/rev/08455e9849f2
branches: trunk
changeset: 781319:08455e9849f2
user: matt <matt%NetBSD.org@localhost>
date: Sat Sep 01 00:07:32 2012 +0000
description:
Some initial iMX.6 support
diffstat:
sys/arch/arm/imx/files.imx6 | 105 +++++++++++++++++++++
sys/arch/arm/imx/imx51_ccm.c | 71 ++++++--------
sys/arch/arm/imx/imx51_ccmreg.h | 6 +-
sys/arch/arm/imx/imx6_intr.h | 172 ++++++++++++++++++++++++++++++++++
sys/arch/arm/imx/imx6_reg.h | 198 ++++++++++++++++++++++++++++++++++++++++
5 files changed, 510 insertions(+), 42 deletions(-)
diffs (truncated from 703 to 300 lines):
diff -r 04af225785aa -r 08455e9849f2 sys/arch/arm/imx/files.imx6
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/files.imx6 Sat Sep 01 00:07:32 2012 +0000
@@ -0,0 +1,105 @@
+# $NetBSD: files.imx6,v 1.1 2012/09/01 00:07:32 matt Exp $
+#
+# Configuration info for the Freescale i.MX6
+#
+
+defparam opt_imx.h MEMSIZE
+defflag opt_imx.h IMX6
+
+define bus_dma_generic
+
+file arch/arm/imx/imx_space.c
+file arch/arm/imx/imx_dma.c bus_dma_generic needs-flag
+
+# iMX6 AXI/AHB bus interface and SoC domains
+device axi { [addr=-1], [size=0], [irq=-1], [irqbase=-1]} : bus_space_generic
+attach axi at mainbus
+file arch/arm/imx/imx6_axi.c axi
+
+# iMX6 Enhanced Periodic Interrupt Timer
+device imxclock
+attach imxclock at axi
+file arch/arm/imx/imxclock.c
+file arch/arm/imx/imx6_clock.c
+
+# Clock Control Module
+device imxccm
+attach imxccm at axi
+file arch/arm/imx/imx6_ccm.c imxccm needs-flag
+
+# frequency of external low frequency clock
+# typically 32000, 32768, or 38400.
+defparam opt_imx6clk.h IMX6_CKIL_FREQ
+
+# frequency of on-chip oscillator. typically 24000000.
+defparam opt_imx6clk.h IMX6_OSC_FREQ
+
+# following parameters are used when imxccm is not configured in the kernel.
+defparam opt_imx6clk.h IMX6_AHBCLK_FREQ
+defparam opt_imx6clk.h IMX6_IPGCLK_FREQ
+
+# iMX GPIO
+#device imxgpio: gpiobus
+attach imxgpio at axi
+#file arch/arm/imx/imxgpio.c imxgpio needs-flag
+#file arch/arm/imx/imx6_gpio.c imxgpio
+
+# iMX IOMUX
+#device imxiomux : bus_space_generic
+#attach imxiomux at axi
+#file arch/arm/imx/imx6_iomux.c imxiomux
+
+# IPU v3 controller
+#device ipu : bus_dma_generic, wsemuldisplaydev, rasops16, rasops8, rasops4, rasops_rotation, vcons
+#file arch/arm/imx/imx6_ipuv3.c ipu needs-flag
+#defflag opt_imx6_ipuv3.h IMXIPUCONSOLE
+#defparam opt_imx6_ipuv3.h IPUV3_DEBUG
+
+# iMX M3IF - Multi Master Memory Interface
+# iMX ESDCTL/MDDRC - Enhanced SDRAM/LPDDR memory controller
+# iMX PCMCIA - PCMCIA memory controller
+# iMX NANDFC - NAND Flash memory controller
+# iMX WEIM - Wireless External Interface Module
+
+# iMX UART
+device imxuart
+attach imxuart at axi
+file arch/arm/imx/imxuart.c imxuart needs-flag
+file arch/arm/imx/imx6_uart.c imxuart
+defflag opt_imxuart.h IMXUARTCONSOLE
+
+# USB controller
+# attach of this driver need to be specified in paltform configuration
+device imxusbc { unit, irq } : bus_dma_generic
+file arch/arm/imx/imx6_usb.c imxusbc
+
+attach ehci at imxusbc with imxehci
+file arch/arm/imx/imxusb.c imxehci
+
+# attach wdc at ahb with wdc_ahb : bus_dma_generic
+# file arch/arm/imx/wdc_axi.c wdc_axi
+
+# SD host controller for SD/MMC
+attach sdhc at axi with sdhc_axi
+file arch/arm/imx/imx6_esdhc.c sdhc_axi
+
+# iic Controler
+# device imxi2c: i2cbus
+# file arch/arm/imx/imx6_i2c.c imxi2c
+
+# attach imxi2c at aips with imxi2c_aips
+# file arch/arm/imx/imxi2c_aips.c imxi2c_aips
+
+# spi bus controlloer
+# device imxspi: spibus
+# file arch/arm/imx/imx6_spi.c imxspi
+
+# Smart Direct Memory Access Controller
+# device imxsdma: dmover_service, bus_dma_generic
+# attach imxsdma at ahb
+# file arch/arm/imx/imxsdma.c imxsdma
+# file arch/arm/imx/imxsdmaprog.c imxsdma
+
+# iis sound Controller (SSI module)
+# device imxi2s {} : bus_dma_generic
+# file arch/arm/imx/imx6_i2s.c imxi2s needs-flag
diff -r 04af225785aa -r 08455e9849f2 sys/arch/arm/imx/imx51_ccm.c
--- a/sys/arch/arm/imx/imx51_ccm.c Sat Sep 01 00:06:54 2012 +0000
+++ b/sys/arch/arm/imx/imx51_ccm.c Sat Sep 01 00:07:32 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/* $NetBSD: imx51_ccm.c,v 1.2 2012/09/01 00:07:32 matt Exp $ */
/*
* Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.2 2012/09/01 00:07:32 matt Exp $");
#include <sys/types.h>
#include <sys/time.h>
@@ -82,6 +82,9 @@
{
struct axi_attach_args *aa = aux;
+ if (ccm_softc != NULL)
+ return 0;
+
if (aa->aa_addr == CCMC_BASE)
return 1;
@@ -91,24 +94,23 @@
static void
imxccm_attach(device_t parent, device_t self, void *aux)
{
+ struct imxccm_softc * const sc = device_private(self);
struct axi_attach_args *aa = aux;
bus_space_tag_t iot = aa->aa_iot;
- int i;
- ccm_softc = device_private(self);
- ccm_softc->sc_dev = self;
- ccm_softc->sc_iot = iot;
+ ccm_softc = sc;
+ sc->sc_dev = self;
+ sc->sc_iot = iot;
- if (bus_space_map(iot, aa->aa_addr, CCMC_SIZE, 0,
- &ccm_softc->sc_ioh)) {
- aprint_error(": can't map\n");
+ if (bus_space_map(iot, aa->aa_addr, CCMC_SIZE, 0, &sc->sc_ioh)) {
+ aprint_error(": can't map registers\n");
return;
}
- for (i=1; i <= IMX51_N_DPLLS; ++i) {
+ for (u_int i=1; i <= IMX51_N_DPLLS; ++i) {
if (bus_space_map(iot, DPLL_BASE(i), DPLL_SIZE, 0,
- &ccm_softc->sc_pll[i-1].pll_ioh)) {
- aprint_error(": can't map\n");
+ &sc->sc_pll[i-1].pll_ioh)) {
+ aprint_error(": can't map pll registers\n");
return;
}
}
@@ -153,7 +155,7 @@
case IMX51CLK_PLL1:
case IMX51CLK_PLL2:
case IMX51CLK_PLL3:
- return ccm_softc->sc_pll[clk-IMX51CLK_PLL1].pll_freq;
+ return ccm_softc->sc_pll[clk - IMX51CLK_PLL1].pll_freq;
case IMX51CLK_PLL1SW:
ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0)
@@ -162,19 +164,17 @@
/* FALLTHROUGH */
case IMX51CLK_PLL1STEP:
ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
- switch ((ccsr & CCSR_STEP_SEL_MASK) >> CCSR_STEP_SEL_SHIFT) {
+ switch (__SHIFTOUT(ccsr, CCSR_STEP_SEL)) {
case 0:
return imx51_get_clock(IMX51CLK_LP_APM);
case 1:
return 0; /* XXX PLL bypass clock */
case 2:
return ccm_softc->sc_pll[2-1].pll_freq /
- (1 + ((ccsr & CCSR_PLL2_DIV_PODF_MASK) >>
- CCSR_PLL2_DIV_PODF_SHIFT));
+ (1 + __SHIFTOUT(ccsr, CCSR_PLL2_DIV_PODF));
case 3:
return ccm_softc->sc_pll[3-1].pll_freq /
- (1 + ((ccsr & CCSR_PLL3_DIV_PODF_MASK) >>
- CCSR_PLL3_DIV_PODF_SHIFT));
+ (1 + __SHIFTOUT(ccsr & CCSR_PLL3_DIV_PODF))
}
/*NOTREACHED*/
case IMX51CLK_PLL2SW:
@@ -206,8 +206,7 @@
else {
freq = 0;
cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
- switch ((cbcmr & CBCMR_PERIPH_APM_SEL_MASK) >>
- CBCMR_PERIPH_APM_SEL_SHIFT) {
+ switch (__SHIFTOUT(cbcmr, CBCMR_PERIPH_APM_SEL)) {
case 0:
freq = imx51_get_clock(IMX51CLK_PLL1SW);
break;
@@ -226,18 +225,15 @@
case IMX51CLK_MAIN_BUS_CLK:
freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
cdcr = bus_space_read_4(iot, ioh, CCMC_CDCR);
- return freq / (cdcr & CDCR_PERIPH_CLK_DVFS_PODF_MASK) >>
- CDCR_PERIPH_CLK_DVFS_PODF_SHIFT;
+ return freq / __SHIFTOUT(cdcr, CDCR_PERIPH_CLK_DVFS_PODF);
case IMX51CLK_AHB_CLK_ROOT:
freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK);
cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
- return freq / (1 + ((cbcdr & CBCDR_AHB_PODF_MASK) >>
- CBCDR_AHB_PODF_SHIFT));
+ return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_AHB_PODF));
case IMX51CLK_IPG_CLK_ROOT:
freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
- return freq / (1 + ((cbcdr & CBCDR_IPG_PODF_MASK) >>
- CBCDR_IPG_PODF_SHIFT));
+ return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_IPG_PODF));
case IMX51CLK_PERCLK_ROOT:
cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
@@ -253,12 +249,9 @@
printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr);
#endif
- freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED1_MASK) >>
- CBCDR_PERCLK_PRED1_SHIFT);
- freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED2_MASK) >>
- CBCDR_PERCLK_PRED2_SHIFT);
- freq /= 1 + ((cbcdr & CBCDR_PERCLK_PODF_MASK) >>
- CBCDR_PERCLK_PODF_SHIFT);
+ freq /= 1 + __SHIFTOUT(cbcdr & CBCDR_PERCLK_PRED1);
+ freq /= 1 + __SHIFTOUT(cbcdr & CBCDR_PERCLK_PRED2);
+ freq /= 1 + __SHIFTOUT(cbcdr & CBCDR_PERCLK_PODF);
return freq;
case IMX51CLK_UART_CLK_ROOT:
cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1);
@@ -268,8 +261,7 @@
printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1);
#endif
- sel = (cscmr1 & CSCMR1_UART_CLK_SEL_MASK) >>
- CSCMR1_UART_CLK_SEL_SHIFT;
+ sel = __SHIFTOUT(cscmr1 & CSCMR1_UART_CLK_SEL);
freq = 0; /* shut up GCC */
switch (sel) {
@@ -283,15 +275,12 @@
break;
}
- return freq / (1 + ((cscdr1 & CSCDR1_UART_CLK_PRED_MASK) >>
- CSCDR1_UART_CLK_PRED_SHIFT)) /
- (1 + ((cscdr1 & CSCDR1_UART_CLK_PODF_MASK) >>
- CSCDR1_UART_CLK_PODF_SHIFT));
+ return freq / (1 + __SHIFTOUT(cscdr1. CSCDR1_UART_CLK_PRED));
+ / (1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PODF));
case IMX51CLK_IPU_HSP_CLK_ROOT:
freq = 0;
cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
- switch ((cbcmr & CBCMR_IPU_HSP_CLK_SEL_MASK) >>
- CBCMR_IPU_HSP_CLK_SEL_SHIFT) {
+ switch (__SHIFTOUT(cbcmr, CBCMR_IPU_HSP_CLK_SEL)) {
case 0:
freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK);
break;
@@ -347,7 +336,7 @@
}
pdf = dp_op & DP_OP_PDF_MASK;
- mfi = max(5, (dp_op & DP_OP_MFI_MASK) >> DP_OP_MFI_SHIFT);
+ mfi = max(5, __SHIFTOUT(dp_op, DP_OP_MFI));
mfd = dp_mfd;
if (dp_mfn & __BIT(26))
/* 27bit signed value */
diff -r 04af225785aa -r 08455e9849f2 sys/arch/arm/imx/imx51_ccmreg.h
--- a/sys/arch/arm/imx/imx51_ccmreg.h Sat Sep 01 00:06:54 2012 +0000
+++ b/sys/arch/arm/imx/imx51_ccmreg.h Sat Sep 01 00:07:32 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_ccmreg.h,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/* $NetBSD: imx51_ccmreg.h,v 1.2 2012/09/01 00:07:32 matt Exp $ */
/*
* Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -32,8 +32,10 @@
/* register offset address */
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