[src/trunk]: src/sys/arch/sparc64/sparc64 s/L_ADDR/L_PCB/, requested by rmind.

[mrg <mrg%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/46575ff90c13
branches:  trunk
changeset: 749279:46575ff90c13
user:      mrg <mrg%NetBSD.org@localhost>
date:      Wed Nov 25 02:34:34 2009 +0000

description:
s/L_ADDR/L_PCB/, requested by rmind.

diffstat:

 sys/arch/sparc64/sparc64/genassym.cf |   4 ++--
 sys/arch/sparc64/sparc64/locore.s    |  10 +++++-----
 2 files changed, 7 insertions(+), 7 deletions(-)

diffs (63 lines):

diff -r c3bc9c816897 -r 46575ff90c13 sys/arch/sparc64/sparc64/genassym.cf
--- a/sys/arch/sparc64/sparc64/genassym.cf      Tue Nov 24 20:11:50 2009 +0000
+++ b/sys/arch/sparc64/sparc64/genassym.cf      Wed Nov 25 02:34:34 2009 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: genassym.cf,v 1.60 2008/09/20 18:29:05 tsutsui Exp $
+#      $NetBSD: genassym.cf,v 1.61 2009/11/25 02:34:34 mrg Exp $
 
 #
 # Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -112,7 +112,7 @@
 define PAGE_SIZE       PAGE_SIZE
 
 # Important offsets into the lwp and proc structs & associated constants
-define L_ADDR                  offsetof(struct lwp, l_addr)
+define L_PCB                   offsetof(struct lwp, l_addr)
 define L_PROC                  offsetof(struct lwp, l_proc)
 define L_TF                    offsetof(struct lwp, l_md.md_tf)
 define L_FPSTATE               offsetof(struct lwp, l_md.md_fpstate)
diff -r c3bc9c816897 -r 46575ff90c13 sys/arch/sparc64/sparc64/locore.s
--- a/sys/arch/sparc64/sparc64/locore.s Tue Nov 24 20:11:50 2009 +0000
+++ b/sys/arch/sparc64/sparc64/locore.s Wed Nov 25 02:34:34 2009 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.s,v 1.292 2009/10/17 20:03:06 nakayama Exp $    */
+/*     $NetBSD: locore.s,v 1.293 2009/11/25 02:34:34 mrg Exp $ */
 
 /*
  * Copyright (c) 1996-2002 Eduardo Horvath
@@ -5062,7 +5062,7 @@
        sethi   %hi(CPUINFO_VA+CI_CURLWP), %l0
        LDPTR   [%l0 + %lo(CPUINFO_VA+CI_CURLWP)], %l0
        set     USPACE - TF_SIZE - CC64FSZ, %l1
-       LDPTR   [%l0 + L_ADDR], %l0
+       LDPTR   [%l0 + L_PCB], %l0
        add     %l1, %l0, %l0
 #ifdef _LP64
        andn    %l0, 0x0f, %l0                  ! Needs to be 16-byte aligned
@@ -5266,7 +5266,7 @@
        sethi   %hi(CPUINFO_VA+CI_IDLELWP), %l0
        LDPTR   [%l0 + %lo(CPUINFO_VA+CI_IDLELWP)], %l0
        set     USPACE - TF_SIZE - CC64FSZ, %l1
-       LDPTR   [%l0 + L_ADDR], %l0
+       LDPTR   [%l0 + L_PCB], %l0
        add     %l0, %l1, %l0
 #ifdef _LP64
        andn    %l0, 0x0f, %l0                  ! Needs to be 16-byte aligned
@@ -6717,7 +6717,7 @@
         sethi  %hi(CPCB), %l6
 
        rdpr    %pstate, %o1                    ! oldpstate = %pstate;
-       LDPTR   [%i0 + L_ADDR], %l5
+       LDPTR   [%i0 + L_PCB], %l5
 
        stx     %i7, [%l5 + PCB_PC]
        stx     %i6, [%l5 + PCB_SP]
@@ -6729,7 +6729,7 @@
 1:
        sethi   %hi(CURLWP), %l7
 
-       LDPTR   [%i1 + L_ADDR], %l1     ! newpcb = l->l_addr;
+       LDPTR   [%i1 + L_PCB], %l1      ! newpcb = l->l_pcb;
 
        /*
         * Load the new lwp.  To load, we must change stacks and