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[src/trunk]: src/sys/arch/powerpc/include/booke Add initial versions of these...
details: https://anonhg.NetBSD.org/src/rev/1d34631a5410
branches: trunk
changeset: 752879:1d34631a5410
user: matt <matt%NetBSD.org@localhost>
date: Tue Mar 09 22:39:32 2010 +0000
description:
Add initial versions of these for BookE.
diffstat:
sys/arch/powerpc/include/booke/Makefile | 11 +
sys/arch/powerpc/include/booke/booke_intr.h | 95 ++++++
sys/arch/powerpc/include/booke/pte.h | 60 ++++
sys/arch/powerpc/include/booke/spr.h | 402 ++++++++++++++++++++++++++++
sys/arch/powerpc/include/booke/trap.h | 57 +++
sys/arch/powerpc/include/booke/vmparam.h | 147 ++++++++++
6 files changed, 772 insertions(+), 0 deletions(-)
diffs (truncated from 796 to 300 lines):
diff -r aa4ee21e121e -r 1d34631a5410 sys/arch/powerpc/include/booke/Makefile
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/powerpc/include/booke/Makefile Tue Mar 09 22:39:32 2010 +0000
@@ -0,0 +1,11 @@
+# $NetBSD: Makefile,v 1.1 2010/03/09 22:39:32 matt Exp $
+
+INCSDIR= /usr/include/powerpc/booke
+
+INCS= booke_intr.h \
+ pmap.h pte.h \
+ spr.h \
+ trap.h \
+ vmparam.h
+
+.include <bsd.kinc.mk>
diff -r aa4ee21e121e -r 1d34631a5410 sys/arch/powerpc/include/booke/booke_intr.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/powerpc/include/booke/booke_intr.h Tue Mar 09 22:39:32 2010 +0000
@@ -0,0 +1,95 @@
+/* $NetBSD: booke_intr.h,v 1.1 2010/03/09 22:39:32 matt Exp $ */
+
+/*-
+ * Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _BOOKE_INTR_H_
+#define _BOOKE_INTR_H_
+
+/* Interrupt priority `levels'. */
+#define IPL_NONE 0 /* nothing */
+#define IPL_SOFTCLOCK 1 /* software clock interrupt */
+#define IPL_SOFTBIO 2 /* software block i/o interrupt */
+#define IPL_SOFTNET 3 /* software network interrupt */
+#define IPL_SOFTSERIAL 4 /* software serial interrupt */
+#define IPL_VM 5 /* memory allocation */
+#define IPL_SCHED 6 /* clock */
+#define IPL_HIGH 7 /* everything */
+#define NIPL 8
+
+/* Interrupt sharing types. */
+#define IST_NONE 0 /* none */
+#define IST_PULSE 1 /* pulsed */
+#define IST_EDGE 2 /* edge-triggered */
+#define IST_LEVEL 3 /* level-triggered */
+
+#ifndef _LOCORE
+
+#define CLKF_BASEPRI(frame) ((frame)->cf_ipl == IPL_NONE)
+
+void *intr_establish(int, int, int, int (*)(void *), void *);
+void intr_disestablish(void *);
+void intr_init(void);
+void ext_intr(void); /* for machdep */
+int splraise(int);
+int spllower(int);
+void splx(int);
+void softintr(int);
+
+extern volatile u_int imask[NIPL];
+extern const int mask_clock; /* for clock.c */
+extern const int mask_statclock; /* for clock.c */
+
+#define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK])
+
+typedef int ipl_t;
+typedef struct {
+ ipl_t _ipl;
+} ipl_cookie_t;
+
+static inline ipl_cookie_t
+makeiplcookie(ipl_t ipl)
+{
+
+ return (ipl_cookie_t){._ipl = ipl};
+}
+
+static inline int
+splraiseipl(ipl_cookie_t icookie)
+{
+
+ return splraise(imask[icookie._ipl]);
+}
+
+#include <sys/spl.h>
+
+#define spl0() spllower(0)
+
+#endif /* !_LOCORE */
+#endif /* !_BOOKE_INTR_H_ */
diff -r aa4ee21e121e -r 1d34631a5410 sys/arch/powerpc/include/booke/pte.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/powerpc/include/booke/pte.h Tue Mar 09 22:39:32 2010 +0000
@@ -0,0 +1,60 @@
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _POWERPC_BOOKE_PTE_H_
+#define _POWERPC_BOOKE_PTE_H_
+
+#ifndef _LOCORE
+typedef __uint32_t pt_entry_t;
+#endif
+
+/*
+ * The PTE format is software and must be translated into the various portions
+ * X W R are separted by single bits so that they can map to the MAS2 bits
+ * UX/UW/UR or SX/SW/SR by a mask and a shift.
+ */
+#define PTE_MAS3_MASK (MAS3_RPN|MAS3_U2)
+#define PTE_MAS2_MASK (MAS2_WIMGE)
+#define PTE_RPN_MASK MAS3_RPN /* MAS3[RPN] */
+#define PTE_RWX_MASK (PTE_xX|PTE_xW|PTE_xR)
+#define PTE_WIRED (MAS3_U0 << 2) /* page is wired (PTE only) */
+#define PTE_xX (MAS3_U0 << 1) /* MAS2[UX] | MAS2[SX] */
+#define PTE_UNSYNCED MAS3_U0 /* page needs isync */
+#define PTE_xW MAS3_U1 /* MAS2[UW] | MAS2[SW] */
+#define PTE_UNMODIFIED MAS3_U2 /* page is unmodified */
+#define PTE_xR MAS3_U3 /* MAS2[UR] | MAS2[SR] */
+#define PTE_RWX_SHIFT 5
+#define PTE_WIMGE_MASK MAS2_WIMGE
+#define PTE_W MAS2_W /* Write-through */
+#define PTE_I MAS2_I /* cache-Inhibited */
+#define PTE_M MAS2_M /* Memory coherence */
+#define PTE_G MAS2_G /* Guarded */
+#define PTE_E MAS2_E /* [Little] Endian */
+
+#endif /* !_POWERPC_BOOKE_PTE_H_ */
diff -r aa4ee21e121e -r 1d34631a5410 sys/arch/powerpc/include/booke/spr.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/powerpc/include/booke/spr.h Tue Mar 09 22:39:32 2010 +0000
@@ -0,0 +1,402 @@
+/* $NetBSD: spr.h,v 1.1 2010/03/09 22:39:32 matt Exp $ */
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas <matt%3am-software.com@localhost>.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _POWERPC_BOOKE_SPR_H_
+#define _POWERPC_BOOKE_SPR_H_
+
+#define PVR_MPCe500 0x8020
+#define PVR_MPCe500v2 0x8021
+#define SVR_MPC8548v1 0x80310010
+#define SVR_MPC8543v1 0x80320010
+#define SVR_MPC8548v1plus 0x80310011
+#define SVR_MPC8543v1plus 0x80320011
+#define SVR_MPC8548v2 0x80310020
+#define SVR_MPC8547v2 0x80310120
+#define SVR_MPC8545v2 0x80310220
+#define SVR_MPC8543v2 0x80320020
+#define SVR_MPC8572 0x80300011
+
+/*
+ * Special Purpose Register declarations.
+ *
+ * The first column in the comments indicates which PowerPC architectures the
+ * SPR is valid on - E for BookE series, 4 for 4xx series,
+ * 6 for 6xx/7xx series and 8 for 8xx and 8xxx (but not 85xx) series.
+ */
+
+#define SPR_PID0 48 /* E4.. 440 Process ID */
+#define SPR_DECAR 54 /* E... Decrementer Auto-reload */
+#define SPR_CSRR0 58 /* E... Critical Save/Restore Reg. 0 */
+#define SPR_CSRR1 59 /* E... Critical Save/Restore Reg. 1 */
+#define SPR_DEAR 61 /* E... Data Exception Address Reg. */
+#define SPR_ESR 62 /* E... Exception Syndrome Register */
+#define ESR_PIL 0x08000000 /* 4: Program ILlegal */
+#define ESR_PPR 0x04000000 /* 5: Program PRivileged */
+#define ESR_PTR 0x02000000 /* 6: Program TRap */
+#define ESR_ST 0x00800000 /* 8: Store operation */
+#define ESR_DLK 0x00200000 /* 10: dcache exception */
+#define ESR_ILK 0x00100000 /* 11: icache exception */
+#define ESR_AP 0x00100000 /* 12: Auxiliary Processor operation exception */
+#define ESR_PUO 0x00100000 /* 13: Program Unimplemented Operation exception */
+#define ESR_BO 0x00020000 /* 14: Byte ordering exception */
+#define ESR_PIE 0x00020000 /* 14: Program Imprecise Exception */
+#define ESR_SPV 0x00000080 /* 24: SPE exception */
+#define ESR_VLEMI 0x00000080 /* 26: VLE exception */
+#define ESR_MIF 0x00000080 /* 30: VLE Misaligned Instruction Fetch */
+#define ESR_XTE 0x00000080 /* 31: eXternal Transaction Error */
+#define SPR_IVPR 63 /* E... Interrupt Vector Prefix Reg. */
+#define SPR_USPRG0 256 /* E4.. User SPR General 0 */
+#define SPR_USPRG3 259 /* E... User SPR General 3 */
+#define SPR_USPRG4 260 /* E... User SPR General 4 */
+#define SPR_USPRG5 261 /* E... User SPR General 5 */
+#define SPR_USPRG6 262 /* E... User SPR General 6 */
+#define SPR_USPRG7 263 /* E... User SPR General 7 */
+#define SPR_RTBL 268 /* E468 Time Base Lower (RO) */
+#define SPR_RTBU 269 /* E468 Time Base Upper (RO) */
+#define SPR_WTBL 284 /* E468 Time Base Lower (WO) */
+#define SPR_WTBU 285 /* E468 Time Base Upper (WO) */
+
+#define SPR_DBSR 304 /* E... Debug Status Register (W1C) */
+#define DBSR_IDE 0x80000000 /* 0: Imprecise debug event */
+#define DBSR_UDE 0x40000000 /* 1: Unconditional debug event */
+#define DBSR_MRR_HARD 0x20000000 /* 2: Most Recent Reset (Hard) */
+#define DBSR_MRR_SOFT 0x10000000 /* 3: Most Recent Reset (Soft) */
+#define DBSR_ICMP 0x08000000 /* 4: Instruction completion debug event */
+#define DBSR_BRT 0x04000000 /* 5: Branch Taken debug event */
+#define DBSR_IRPT 0x02000000 /* 6: Interrupt Taken debug event */
+#define DBSR_TRAP 0x01000000 /* 7: Trap Instruction debug event */
+#define DBSR_IAC1 0x00800000 /* 8: IAC1 debug event */
+#define DBSR_IAC2 0x00400000 /* 9: IAC2 debug event */
+#define DBSR_DR1 0x00080000 /* 12: DAC1 Read debug event */
+#define DBSR_DW1 0x00040000 /* 13: DAC1 Write debug event */
+#define DBSR_DR2 0x00020000 /* 14: DAC2 Read debug event */
+#define DBSR_DW2 0x00010000 /* 15: DAC2 Write debug event */
+#define DBSR_RET 0x00008000 /* 16: Return debug event */
+#define SPR_DBCR0 308 /* E... Debug Control Register 0 */
+#define DBCR0_EDM 0x80000000 /* 0: External Debug Mode */
+#define DBCR0_IDM 0x40000000 /* 1: Internal Debug Mode */
+#define DBCR0_RST_MASK 0x30000000 /* 2..3: ReSeT */
+#define DBCR0_RST_NONE 0x00000000 /* No action */
+#define DBCR0_RST_CORE 0x10000000 /* Core reset */
+#define DBCR0_RST_CHIP 0x20000000 /* Chip reset */
+#define DBCR0_RST_SYSTEM 0x30000000 /* System reset */
+#define DBCR0_IC 0x08000000 /* 4: Instruction Completion debug event */
+#define DBCR0_BT 0x04000000 /* 5: Branch Taken debug event */
+#define DBCR0_EDE 0x02000000 /* 6: Exception Debug Event */
+#define DBCR0_TDE 0x01000000 /* 7: Trap Debug Event */
+#define DBCR0_IA1 0x00800000 /* 8: IAC (Instruction Address Compare) 1 debug event */
+#define DBCR0_IA2 0x00400000 /* 9: IAC 2 debug event */
+#define DBCR0_IA12 0x00200000 /* 10: Instruction Address Range Compare 1-2 */
+#define DBCR0_IA12X 0x00100000 /* 11: IA12 eXclusive */
+#define DBCR0_IA3 0x00080000 /* 12: IAC 3 debug event */
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