[src/trunk]: src/sys/arch/powerpc enable FAST_SOFTINTR support for all ports ...

[macallan <macallan%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/eaf3a23fd423
branches:  trunk
changeset: 766115:eaf3a23fd423
user:      macallan <macallan%NetBSD.org@localhost>
date:      Thu Jun 16 02:43:42 2011 +0000

description:
enable FAST_SOFTINTR support for all ports that use powerpc/pic/
This has been successfully tested on macppc
TODO:
- ibm4xx needs to be adapted
- SMP doesn't work yet, 2nd CPU crashes when trying to leave the idle loop

diffstat:

 sys/arch/powerpc/include/intr.h  |  34 ++++++++++--------
 sys/arch/powerpc/oea/genassym.cf |   4 +-
 sys/arch/powerpc/pic/files.pic   |   4 +-
 sys/arch/powerpc/pic/intr.c      |  72 +++++++++++++++++++--------------------
 sys/arch/powerpc/pic/pic_subr.c  |  49 +++++++++++++++++++++++++++
 sys/arch/powerpc/powerpc/clock.c |   6 +-
 6 files changed, 111 insertions(+), 58 deletions(-)

diffs (truncated from 390 to 300 lines):

diff -r 4322cabb3a93 -r eaf3a23fd423 sys/arch/powerpc/include/intr.h
--- a/sys/arch/powerpc/include/intr.h   Thu Jun 16 01:04:15 2011 +0000
+++ b/sys/arch/powerpc/include/intr.h   Thu Jun 16 02:43:42 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: intr.h,v 1.5 2010/04/25 12:26:07 kiyohara Exp $ */
+/*     $NetBSD: intr.h,v 1.6 2011/06/16 02:43:42 macallan Exp $ */
 
 /*-
  * Copyright (c) 2007 Michael Lorenz
@@ -26,16 +26,22 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#ifndef _LOCORE
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intr.h,v 1.5 2010/04/25 12:26:07 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intr.h,v 1.6 2011/06/16 02:43:42 macallan Exp $");
+#endif
 
 #ifndef POWERPC_INTR_MACHDEP_H
 #define POWERPC_INTR_MACHDEP_H
 
+#define        __HAVE_FAST_SOFTINTS    1
+
+#ifndef _LOCORE
 void *intr_establish(int, int, int, int (*)(void *), void *);
 void intr_disestablish(void *);
 const char *intr_typename(int);
 void genppc_cpu_configure(void);
+#endif
 
 /* Interrupt priority `levels'. */
 #define        IPL_NONE        0       /* nothing */
@@ -54,6 +60,10 @@
 #define        IST_EDGE        2       /* edge-triggered */
 #define        IST_LEVEL       3       /* level-triggered */
 
+#ifdef _LOCORE
+#define splhigh __splhigh
+#endif
+
 #ifndef _LOCORE
 /*
  * Interrupt handler chains.  intr_establish() inserts a handler into
@@ -70,7 +80,11 @@
 int splraise(int);
 int spllower(int);
 void splx(int);
-void softintr(int);
+
+void softint_fast_dispatch(struct lwp *, int);
+
+#define softint_init_md        powerpc_softint_init_md
+#define softint_trigger                powerpc_softint_trigger
 
 typedef u_int imask_t;
 extern imask_t imask[];
@@ -83,18 +97,6 @@
 
 #define MS_PENDING(p)  (31 - cntlzw(p))
 
-/* Soft interrupt masks. */
-#define SIR_CLOCK      27
-#define SIR_BIO                28
-#define SIR_NET                29
-#define SIR_SERIAL     30
-#define SPL_CLOCK      31
-
-#define setsoftclock() softintr(SIR_CLOCK)
-#define setsoftbio()   softintr(SIR_BIO)
-#define setsoftnet()   softintr(SIR_NET)
-#define setsoftserial()        softintr(SIR_SERIAL)
-
 #define spl0()         spllower(0)
 
 typedef int ipl_t;
@@ -113,7 +115,7 @@
 splraiseipl(ipl_cookie_t icookie)
 {
 
-       return splraise(imask[icookie._ipl]);
+       return splraise(icookie._ipl);
 }
 
 #include <sys/spl.h>
diff -r 4322cabb3a93 -r eaf3a23fd423 sys/arch/powerpc/oea/genassym.cf
--- a/sys/arch/powerpc/oea/genassym.cf  Thu Jun 16 01:04:15 2011 +0000
+++ b/sys/arch/powerpc/oea/genassym.cf  Thu Jun 16 02:43:42 2011 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: genassym.cf,v 1.18 2011/06/05 16:52:25 matt Exp $
+#      $NetBSD: genassym.cf,v 1.19 2011/06/16 02:43:43 macallan Exp $
 
 #
 # Copyright (C) 1995, 1996 Wolfgang Solfrank.
@@ -217,6 +217,7 @@
 define L_MD_ASTPENDING offsetof(struct lwp, l_md.md_astpending)
 define L_MD_UTF        offsetof(struct lwp, l_md.md_utf)
 define L_PROC          offsetof(struct lwp, l_proc)
+define L_CTXSWTCH      offsetof(struct lwp, l_ctxswtch)
 
 define P_MD_SYSCALL    offsetof(struct proc, p_md.md_syscall)
 
@@ -232,6 +233,7 @@
 define CI_IPKDBSAVE    offsetof(struct cpu_info, ci_ipkdbsave)
 define CI_DISISAVE     offsetof(struct cpu_info, ci_disisave)
 define CI_IDLESPIN     offsetof(struct cpu_info, ci_idlespin)
+define CI_MTX_COUNT    offsetof(struct cpu_info, ci_mtx_count)
 
 define CPUSAVE_R28     CPUSAVE_R28*sizeof(register_t)
 define CPUSAVE_R29     CPUSAVE_R29*sizeof(register_t)
diff -r 4322cabb3a93 -r eaf3a23fd423 sys/arch/powerpc/pic/files.pic
--- a/sys/arch/powerpc/pic/files.pic    Thu Jun 16 01:04:15 2011 +0000
+++ b/sys/arch/powerpc/pic/files.pic    Thu Jun 16 02:43:42 2011 +0000
@@ -1,9 +1,11 @@
 # 
-#      $NetBSD: files.pic,v 1.5 2011/06/05 16:52:26 matt Exp $
+#      $NetBSD: files.pic,v 1.6 2011/06/16 02:43:43 macallan Exp $
 #
 # generic PIC abstraction
 
 file arch/powerpc/pic/intr.c
+file arch/powerpc/pic/pic_subr.c
+
 defflag opt_pic.h PIC_DEBUG
 
 define pic_openpic
diff -r 4322cabb3a93 -r eaf3a23fd423 sys/arch/powerpc/pic/intr.c
--- a/sys/arch/powerpc/pic/intr.c       Thu Jun 16 01:04:15 2011 +0000
+++ b/sys/arch/powerpc/pic/intr.c       Thu Jun 16 02:43:42 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: intr.c,v 1.11 2011/06/05 16:52:26 matt Exp $ */
+/*     $NetBSD: intr.c,v 1.12 2011/06/16 02:43:43 macallan Exp $ */
 
 /*-
  * Copyright (c) 2007 Michael Lorenz
@@ -27,10 +27,12 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.11 2011/06/05 16:52:26 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.12 2011/06/16 02:43:43 macallan Exp $");
 
 #include "opt_multiprocessor.h"
 
+#define __INTR_PRIVATE
+
 #include <sys/param.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
@@ -47,6 +49,10 @@
 #include <arch/powerpc/pic/ipivar.h>
 #endif
 
+#ifdef __HAVE_FAST_SOFTINTS
+#include <powerpc/softint.h>
+#endif
+
 #define MAX_PICS       8       /* 8 PICs ought to be enough for everyone */
 
 #define        LEGAL_VIRQ(x)   ((x) >= 0 && (x) < NVIRQ)
@@ -353,19 +359,6 @@
        }
 
        /*
-        * IPL_CLOCK should mask clock interrupt even if interrupt handler
-        * is not registered.
-        */
-       imask[IPL_CLOCK] |= 1ULL << SPL_CLOCK;
-
-       /*
-        * Initialize soft interrupt masks to block themselves.
-        */
-       imask[IPL_SOFTCLOCK] = 1ULL << SIR_CLOCK;
-       imask[IPL_SOFTNET] = 1ULL << SIR_NET;
-       imask[IPL_SOFTSERIAL] = 1ULL << SIR_SERIAL;
-
-       /*
         * IPL_NONE is used for hardware interrupts that are never blocked,
         * and do not block anything else.
         */
@@ -483,12 +476,14 @@
 
        pcpl = ci->ci_cpl;
 #ifdef __HAVE_FAST_SOFTINTS
+#if 0
 again:
 #endif
+#endif
 
        /* Do now unmasked pendings */
        ci->ci_idepth++;
-       while ((hwpend = (ci->ci_ipending & ~pcpl & HWIRQ_MASK)) != 0) {
+       while ((hwpend = (ci->ci_ipending & ~imask[pcpl] & HWIRQ_MASK)) != 0) {
                /* Get most significant pending bit */
                irq = MS_PENDING(hwpend);
                KASSERT(irq <= virq_max);
@@ -500,7 +495,7 @@
                is = &intrsources[irq];
                pic = is->is_pic;
 
-               splraise(is->is_mask);
+               splraise(is->is_level);
                mtmsr(emsr);
                ih = is->is_hand;
                while (ih) {
@@ -530,6 +525,7 @@
        ci->ci_idepth--;
 
 #ifdef __HAVE_FAST_SOFTINTS
+#if 0
        if ((ci->ci_ipending & ~pcpl) & (1ULL << SIR_SERIAL)) {
                ci->ci_ipending &= ~(1ULL << SIR_SERIAL);
                splsoftserial();
@@ -560,6 +556,16 @@
                ci->ci_ev_softclock.ev_count++;
                goto again;
        }
+#else
+       const u_int softints = (ci->ci_data.cpu_softints << pcpl) & IPL_SOFTMASK;
+
+       if (__predict_false(softints != 0)) {
+               splhigh();
+               powerpc_softint(ci, pcpl,
+                   (vaddr_t)__builtin_return_address(0));
+               ci->ci_cpl = pcpl;
+       }
+#endif
 #endif
 
        ci->ci_cpl = pcpl;      /* Don't use splx... we are here already! */
@@ -610,7 +616,7 @@
        r_imen = 1ULL << irq;
        is = &intrsources[irq];
 
-       if ((pcpl & r_imen) != 0) {
+       if ((imask[pcpl] & r_imen) != 0) {
 
                ci->ci_ipending |= r_imen; /* Masked! Mark this as pending */
                pic->pic_disable_irq(pic, realirq);
@@ -620,7 +626,7 @@
                ci->ci_ipending &= ~r_imen;
                ci->ci_idepth++;
 
-               splraise(is->is_mask);
+               splraise(is->is_level);
                mtmsr(msr | PSL_EE);
                ih = is->is_hand;
                bail = 0;
@@ -677,11 +683,13 @@
        struct cpu_info *ci = curcpu();
        int ocpl;
 
+       if (ncpl == ci->ci_cpl) return ncpl;
        __asm volatile("sync; eieio");  /* don't reorder.... */
-
        ocpl = ci->ci_cpl;
-       ci->ci_cpl = ocpl | ncpl;
+       KASSERT(ncpl < NIPL);
+       ci->ci_cpl = max(ncpl, ocpl);
        __asm volatile("sync; eieio");  /* reorder protect */
+       __insn_barrier();
        return ocpl;
 }
 
@@ -690,9 +698,11 @@
 {
        struct cpu_info *ci = curcpu();
 
+       __insn_barrier();
        __asm volatile("sync; eieio");  /* reorder protect */
        ci->ci_cpl = ncpl;
-       if (ci->ci_ipending & ~ncpl)
+       if ((ci->ci_ipending & ~imask[ncpl]) ||
+          ((ci->ci_data.cpu_softints << ncpl) & IPL_SOFTMASK))
                pic_do_pending_int();
        __asm volatile("sync; eieio");  /* reorder protect */
 }
@@ -703,29 +713,17 @@
        struct cpu_info *ci = curcpu();
        int ocpl;
 
+       __insn_barrier();
        __asm volatile("sync; eieio");  /* reorder protect */
        ocpl = ci->ci_cpl;
        ci->ci_cpl = ncpl;
-       if (ci->ci_ipending & ~ncpl)
+       if ((ci->ci_ipending & ~imask[ncpl]) ||
+          ((ci->ci_data.cpu_softints << ncpl) & IPL_SOFTMASK))
                pic_do_pending_int();
        __asm volatile("sync; eieio");  /* reorder protect */
        return ocpl;
 }
 
-/* Following code should be implemented with lwarx/stwcx to avoid
- * the disable/enable. i need to read the manual once more.... */
-void
-softintr(int ipl)
-{
-       struct cpu_info *ci = curcpu();
-       int msrsave;