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[src/trunk]: src/sys/arch/powerpc Reap the ci_ev_soft* evcnts since every var...



details:   https://anonhg.NetBSD.org/src/rev/be4c8531ff16
branches:  trunk
changeset: 766353:be4c8531ff16
user:      matt <matt%NetBSD.org@localhost>
date:      Tue Jun 21 04:21:16 2011 +0000

description:
Reap the ci_ev_soft* evcnts since every variant implements __HAVE_FAST_SOFTINTS

diffstat:

 sys/arch/powerpc/booke/booke_machdep.c |    8 -
 sys/arch/powerpc/ibm4xx/cpu.c          |  361 ++++++++++++++++----------------
 sys/arch/powerpc/include/cpu.h         |   19 +-
 sys/arch/powerpc/oea/cpu_subr.c        |   10 +-
 4 files changed, 191 insertions(+), 207 deletions(-)

diffs (truncated from 553 to 300 lines):

diff -r 992f7ad97eaa -r be4c8531ff16 sys/arch/powerpc/booke/booke_machdep.c
--- a/sys/arch/powerpc/booke/booke_machdep.c    Tue Jun 21 04:19:22 2011 +0000
+++ b/sys/arch/powerpc/booke/booke_machdep.c    Tue Jun 21 04:21:16 2011 +0000
@@ -341,14 +341,6 @@
                NULL, xname, "late clock");
        evcnt_attach_dynamic_nozero(&cpu->cpu_ev_exec_trap_sync, EVCNT_TYPE_TRAP,
                NULL, xname, "exec pages synced (trap)");
-#ifndef __HAVE_FAST_SOFTINTS
-       evcnt_attach_dynamic_nozero(&ci->ci_ev_softclock, EVCNT_TYPE_INTR,
-               NULL, xname, "soft clock");
-       evcnt_attach_dynamic_nozero(&ci->ci_ev_softnet, EVCNT_TYPE_INTR,
-               NULL, xname, "soft net");
-       evcnt_attach_dynamic_nozero(&ci->ci_ev_softserial, EVCNT_TYPE_INTR,
-               NULL, xname, "soft serial");
-#endif
        evcnt_attach_dynamic_nozero(&ci->ci_ev_traps, EVCNT_TYPE_TRAP,
                NULL, xname, "traps");
        evcnt_attach_dynamic_nozero(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP,
diff -r 992f7ad97eaa -r be4c8531ff16 sys/arch/powerpc/ibm4xx/cpu.c
--- a/sys/arch/powerpc/ibm4xx/cpu.c     Tue Jun 21 04:19:22 2011 +0000
+++ b/sys/arch/powerpc/ibm4xx/cpu.c     Tue Jun 21 04:21:16 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu.c,v 1.31 2011/06/18 08:21:20 matt Exp $    */
+/*     $NetBSD: cpu.c,v 1.32 2011/06/21 04:21:16 matt Exp $    */
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.31 2011/06/18 08:21:20 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.32 2011/06/21 04:21:16 matt Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -55,29 +55,160 @@
        u_int version;
        u_int mask;
        const char *name;
+       struct cache_info ci;
 };
+
 static const struct cputab models[] = {
-       { PVR_401A1,    0xffff0000,     "401A1"         },
-       { PVR_401B2,    0xffff0000,     "401B21"        },
-       { PVR_401C2,    0xffff0000,     "401C2"         },
-       { PVR_401D2,    0xffff0000,     "401D2"         },
-       { PVR_401E2,    0xffff0000,     "401E2"         },
-       { PVR_401F2,    0xffff0000,     "401F2"         },
-       { PVR_401G2,    0xffff0000,     "401G2"         },
-       { PVR_403,      0xffff0000,     "403"           },
-       { PVR_405GP,    0xffff0000,     "405GP"         },
-       { PVR_405GPR,   0xffff0000,     "405GPr"        },
-       { PVR_405D5X1,  0xfffff000,     "Xilinx Virtex II Pro"  },
-       { PVR_405D5X2,  0xfffff000,     "Xilinx Virtex 4 FX"    },
-       { PVR_405EX,    0xffff0000,     "405EX"         },
-       { 0,            0,              NULL            }
+       {
+               .version = PVR_401A1, 
+               .mask = 0xffff0000,
+               .name = "401A1",
+               .ci = {
+                       .dcache_size = 1024,
+                       .dcache_line_size = 16,
+                       .icache_size = 2848,
+                       .icache_line_size = 16,
+               }
+       }, {
+               .version = PVR_401B2, 
+               .mask = 0xffff0000,
+               .name = "401B21",
+               .ci = {
+                       .dcache_size = 8192,
+                       .dcache_line_size = 16,
+                       .icache_size = 16384,
+                       .icache_line_size = 16,
+               }
+       }, {
+               .version = PVR_401C2, 
+               .mask = 0xffff0000,
+               .name = "401C2",
+               .ci = {
+                       .dcache_size = 8192,
+                       .dcache_line_size = 16,
+                       .icache_size = 0,
+                       .icache_line_size = 16,
+               }
+       }, {
+               .version = PVR_401D2, 
+               .mask = 0xffff0000,
+               .name = "401D2",
+               .ci = {
+                       .dcache_size = 2848,
+                       .dcache_line_size = 16,
+                       .icache_size = 4096,
+                       .icache_line_size = 16,
+               }
+       }, {
+               .version = PVR_401E2, 
+               .mask = 0xffff0000,
+               .name = "401E2",
+               .ci = {
+                       .dcache_size = 0,
+                       .dcache_line_size = 16,
+                       .icache_size = 0,
+                       .icache_line_size = 16,
+               }
+       }, {
+               .version = PVR_401F2, 
+               .mask = 0xffff0000,
+               .name = "401F2",
+               .ci = {
+                       .dcache_size = 2048,
+                       .dcache_line_size = 16,
+                       .icache_size = 2848,
+                       .icache_line_size = 16,
+               }
+       }, {
+               .version = PVR_401G2, 
+               .mask = 0xffff0000,
+               .name = "401G2",
+               .ci = {
+                       .dcache_size = 2848,
+                       .dcache_line_size = 16,
+                       .icache_size = 8192,
+                       .icache_line_size = 16,
+               }
+       }, {
+               .version = PVR_403, 
+               .mask = 0xffff0000,
+               .name = "403",
+               .ci = {
+                       .dcache_size = 8192,
+                       .dcache_line_size = 16,
+                       .icache_size = 16384,
+                       .icache_line_size = 16,
+               }
+       }, {
+               .version = PVR_405GP, 
+               .mask = 0xffff0000,
+               .name = "405GP",
+               .ci = {
+                       .dcache_size = 8192,
+                       .dcache_line_size = 32,
+                       .icache_size = 8192,
+                       .icache_line_size = 32,
+               }
+       }, {
+               .version = PVR_405GPR, 
+               .mask = 0xffff0000,
+               .name = "405GPr",
+               .ci = {
+                       .dcache_size = 16384,
+                       .dcache_line_size = 32,
+                       .icache_size = 16384,
+                       .icache_line_size = 32,
+               }
+       }, {
+               .version = PVR_405D5X1, 
+               .mask = 0xfffff000, 
+               .name = "Xilinx Virtex II Pro",
+               .ci = {
+                       .dcache_size = 16384,
+                       .dcache_line_size = 32,
+                       .icache_size = 16384,
+                       .icache_line_size = 32,
+               }
+       }, {
+               .version = PVR_405D5X2, 
+               .mask = 0xfffff000, 
+               .name = "Xilinx Virtex 4 FX",
+               .ci = {
+                       .dcache_size = 16384,
+                       .dcache_line_size = 32,
+                       .icache_size = 16384,
+                       .icache_line_size = 32,
+               }
+       }, {
+               .version = PVR_405EX, 
+               .mask = 0xffff0000, 
+               .name = "405EX",
+               .ci = {
+                       .dcache_size = 16384,
+                       .dcache_line_size = 32,
+                       .icache_size = 16384,
+                       .icache_line_size = 32,
+               }
+       }, {
+               .version = 0,
+               .mask = 0,
+               .name = NULL,
+               .ci = {
+                       /*
+                        * Unknown CPU type.  For safety we'll specify a
+                        * cache with a 4-byte line size.  That way cache
+                        * flush routines won't miss any lines.
+                        */
+                       .dcache_line_size = 4,
+                       .icache_line_size = 4,
+               },
+       },
 };
 
 static int     cpumatch(device_t, cfdata_t, void *);
 static void    cpuattach(device_t, device_t, void *);
 
-CFATTACH_DECL_NEW(cpu, 0,
-    cpumatch, cpuattach, NULL, NULL);
+CFATTACH_DECL_NEW(cpu, 0, cpumatch, cpuattach, NULL, NULL);
 
 int ncpus;
 
@@ -88,19 +219,13 @@
                    NULL, "cpu0", "clock"),
                .ci_ev_statclock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR,
                    NULL, "cpu0", "stat clock"),
-               .ci_ev_softclock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR,
-                   NULL, "cpu0", "soft clock"),
-               .ci_ev_softnet = EVCNT_INITIALIZER(EVCNT_TYPE_INTR,
-                   NULL, "cpu0", "soft net"),
-               .ci_ev_softserial = EVCNT_INITIALIZER(EVCNT_TYPE_INTR,
-                   NULL, "cpu0", "soft serial"),
                .ci_curlwp = &lwp0,
        }
 };
 
 char cpu_model[80];
 
-int cpufound = 0;
+bool cpufound;
 
 static int
 cpumatch(device_t parent, cfdata_t cf, void *aux)
@@ -117,8 +242,8 @@
 static void
 cpuattach(device_t parent, device_t self, void *aux)
 {
-       const struct cputab *cp = models;
-       u_int pvr;
+       struct cpu_info * const ci = curcpu();
+       const struct cputab *cp;
        u_int processor_freq;
        prop_number_t freq;
 
@@ -126,36 +251,35 @@
        KASSERT(freq != NULL);
        processor_freq = (unsigned int) prop_number_integer_value(freq);
 
-       cpufound++;
+       cpufound = true;
        ncpus++;
 
-       pvr = mfpvr();
-       while (cp->name) {
-               if ((pvr & cp->mask) == cp->version)
+       const u_int pvr = mfpvr();
+       for (cp = models; cp->name != NULL; cp++) {
+               if ((pvr & cp->mask) == cp->version) {
+                       strcpy(cpu_model, cp->name);
                        break;
-               cp++;
+               }
        }
-       if (cp->name)
-               strcpy(cpu_model, cp->name);
-       else
+       if (__predict_false(cp->name == NULL))
                sprintf(cpu_model, "Version 0x%x", pvr);
 
-       printf(": %dMHz %s (PVR 0x%x)\n", processor_freq / 1000 / 1000,
-           cp->name ? cp->name : "unknown model", pvr);
+       aprint_normal(": %uMHz %s (PVR 0x%x)\n",
+           (processor_freq + 500000) / 1000000,
+           (cp->name != NULL ? cpu_model : "unknown model"),
+           pvr);
 
        cpu_probe_cache();
 
        /* We would crash later on anyway so just make the reason obvious */
-       if (curcpu()->ci_ci.icache_size == 0 &&
-           curcpu()->ci_ci.dcache_size == 0)
-               panic("%s could not detect cache size", device_xname(self));
+       if (ci->ci_ci.icache_size == 0 && ci->ci_ci.dcache_size == 0)
+               panic("%s: %s: could not detect cache size",
+                   __func__, device_xname(self));
 
-       printf("%s: Instruction cache size %d line size %d\n",
-           device_xname(self),
-           curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size);
-       printf("%s: Data cache size %d line size %d\n",
-           device_xname(self),
-           curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size);
+       aprint_normal_dev(self, "%uKB/%uB L1 instruction cache\n",
+           ci->ci_ci.icache_size / 1024, ci->ci_ci.icache_line_size);
+       aprint_normal_dev(self, "%uKB/%uB L1 data cache\n",
+           ci->ci_ci.dcache_size / 1024, ci->ci_ci.dcache_line_size);
 }
 
 /*



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