[src/matt-nb6-plus]: src/sys/arch/arm/arm32 Sync with HEAD.

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/bd9aa05adf96
branches:  matt-nb6-plus
changeset: 774559:bd9aa05adf96
user:      matt <matt%NetBSD.org@localhost>
date:      Thu Feb 14 08:24:58 2013 +0000

description:
Sync with HEAD.

diffstat:

 sys/arch/arm/arm32/bus_dma.c |  8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diffs (46 lines):

diff -r bd9f9cbdb091 -r bd9aa05adf96 sys/arch/arm/arm32/bus_dma.c
--- a/sys/arch/arm/arm32/bus_dma.c      Thu Feb 14 08:09:00 2013 +0000
+++ b/sys/arch/arm/arm32/bus_dma.c      Thu Feb 14 08:24:58 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: bus_dma.c,v 1.54.10.4 2013/02/14 08:08:18 matt Exp $   */
+/*     $NetBSD: bus_dma.c,v 1.54.10.5 2013/02/14 08:24:58 matt Exp $   */
 
 /*-
  * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
 #define _ARM32_BUS_DMA_PRIVATE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.54.10.4 2013/02/14 08:08:18 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.54.10.5 2013/02/14 08:24:58 matt Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -763,11 +763,11 @@
                const size_t line_size = arm_dcache_align;
                const size_t line_mask = arm_dcache_align_mask;
                vsize_t misalignment = va & line_mask;
-               STAT_INCR(sync_preread);
                if (misalignment) {
                        va -= misalignment;
                        pa -= misalignment;
                        len += misalignment;
+                       STAT_INCR(sync_preread_begin);
                        cpu_dcache_wbinv_range(va, line_size);
                        cpu_sdcache_wbinv_range(va, pa, line_size);
                        if (len <= line_size)
@@ -779,12 +779,14 @@
                misalignment = len & line_mask;
                len -= misalignment;
                if (len > 0) {
+                       STAT_INCR(sync_preread);
                        cpu_dcache_inv_range(va, len);
                        cpu_sdcache_inv_range(va, pa, len);
                }
                if (misalignment) {
                        va += len;
                        pa += len;
+                       STAT_INCR(sync_preread_tail);
                        cpu_dcache_wbinv_range(va, line_size);
                        cpu_sdcache_wbinv_range(va, pa, line_size);
                }