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[src/trunk]: src/sys/arch/arm/include Add NSACR
details: https://anonhg.NetBSD.org/src/rev/6da5d6f0a4d3
branches: trunk
changeset: 794823:6da5d6f0a4d3
user: matt <matt%NetBSD.org@localhost>
date: Wed Mar 26 01:14:52 2014 +0000
description:
Add NSACR
diffstat:
sys/arch/arm/include/armreg.h | 10 +++++++++-
1 files changed, 9 insertions(+), 1 deletions(-)
diffs (31 lines):
diff -r bf67e1a7b63e -r 6da5d6f0a4d3 sys/arch/arm/include/armreg.h
--- a/sys/arch/arm/include/armreg.h Tue Mar 25 21:07:59 2014 +0000
+++ b/sys/arch/arm/include/armreg.h Wed Mar 26 01:14:52 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.93 2014/03/07 05:30:08 matt Exp $ */
+/* $NetBSD: armreg.h,v 1.94 2014/03/26 01:14:52 matt Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -387,6 +387,13 @@
#define CPACR_RESERVED 2
#define CPACR_ALL 3 /* Privileged and User mode access */
+/* ARMv6/ARMv7 Non-Secure Access Control Register (CP15, 0, c1, c1, 2) */
+#define NSACR_SMP 0x00040000 /* ACTRL.SMP is writeable (!A8) */
+#define NSACR_L2ERR 0x00020000 /* L2ECTRL is writeable (!A8) */
+#define NSACR_ASEDIS 0x00008000 /* Deny Advanced SIMD Ext. */
+#define NSACR_D32DIS 0x00004000 /* Deny VFP regs 15-31 */
+#define NSACR_CPn(n) (1 << (n)) /* NonSecure access allowed */
+
/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */
#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */
#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */
@@ -895,6 +902,7 @@
ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */
ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */
+ARMREG_READ_INLINE(nsacr, "p15,0,%0,c1,c1,2") /* Non-Secure Access Control Register */
/* cp15 c2 registers */
ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
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