[src/trunk]: src/sys/arch/evbarm/marvell Add hook to set L2 cache to write-th...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/cf2e7d7bfe72
branches:  trunk
changeset: 795469:cf2e7d7bfe72
user:      matt <matt%NetBSD.org@localhost>
date:      Mon Apr 14 20:53:28 2014 +0000

description:
Add hook to set L2 cache to write-through

diffstat:

 sys/arch/evbarm/marvell/marvell_start.S |  13 +++++++++++--
 1 files changed, 11 insertions(+), 2 deletions(-)

diffs (34 lines):

diff -r 427b96bf1060 -r cf2e7d7bfe72 sys/arch/evbarm/marvell/marvell_start.S
--- a/sys/arch/evbarm/marvell/marvell_start.S   Mon Apr 14 20:50:46 2014 +0000
+++ b/sys/arch/evbarm/marvell/marvell_start.S   Mon Apr 14 20:53:28 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: marvell_start.S,v 1.5 2014/01/29 04:27:26 kiyohara Exp $ */
+/*     $NetBSD: marvell_start.S,v 1.6 2014/04/14 20:53:28 matt Exp $ */
 /*
  * Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation.
  * All rights reserved.
@@ -66,7 +66,7 @@
 #include <evbarm/marvell/marvellreg.h>
 #include "assym.h"
 
-RCSID("$NetBSD: marvell_start.S,v 1.5 2014/01/29 04:27:26 kiyohara Exp $")
+RCSID("$NetBSD: marvell_start.S,v 1.6 2014/04/14 20:53:28 matt Exp $")
 
 #ifndef SDRAM_START
 #define SDRAM_START    0x00000000
@@ -124,6 +124,15 @@
        mrc     p15, 1, r5, c15, c1, 0  @ Get Marvell Extra Features Register
        bic     r5, r5, #0x00400000     @ disable L2 cache
        mcr     p15, 1, r5, c15, c1, 0
+
+#ifdef SHEEVA_L2_CACHE_WT
+       /* L2 WT Mode */
+       ldr     r2, =0xf1020128         /* CPU L2 Configuration Register */
+       ldr     r3, [r2]
+       bic     r3, r3, #0x10           /* Force Write Through */
+       str     r3, [r2]
+#endif
+
 1:
 
        /* save u-boot's args */