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[src/trunk]: src/sys/arch/arm/allwinner Files for allwinner a20/a10 (need to ...
details: https://anonhg.NetBSD.org/src/rev/40d88179dbbf
branches: trunk
changeset: 789697:40d88179dbbf
user: matt <matt%NetBSD.org@localhost>
date: Tue Sep 03 18:02:26 2013 +0000
description:
Files for allwinner a20/a10 (need to compile stuff in evbarm/cubie)
diffstat:
sys/arch/arm/allwinner/awin_intr.h | 137 ++++++++++++
sys/arch/arm/allwinner/awin_reg.h | 398 +++++++++++++++++++++++++++++++++++++
sys/arch/arm/allwinner/awin_var.h | 42 +++
sys/arch/arm/allwinner/files.awin | 101 +++++++++
4 files changed, 678 insertions(+), 0 deletions(-)
diffs (truncated from 694 to 300 lines):
diff -r 7ae4b7bc6882 -r 40d88179dbbf sys/arch/arm/allwinner/awin_intr.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/allwinner/awin_intr.h Tue Sep 03 18:02:26 2013 +0000
@@ -0,0 +1,137 @@
+/* $NetBSD: awin_intr.h,v 1.1 2013/09/03 18:02:26 matt Exp $ */
+/*-
+ * Copyright (c) 2013 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_ALLWINNER_AWIN_INTR_H_
+#define _ARM_ALLWINNER_AWIN_INTR_H_
+
+#define PIC_MAXSOURCES 128
+#define PIC_MAXMAXSOURCES 256
+
+/*
+ * The Allwinner can use a generic interrupt controller so pull in that stuff.
+ */
+#include <arm/cortex/gic_intr.h>
+#include <arm/cortex/a9tmr_intr.h> /* A7/A9/A15 Timer PPIs */
+
+/*
+ * There are for the A20 but the A10 are the same but offset by 32 less.
+ */
+#define AWIN_IRQ_UART0 33
+#define AWIN_IRQ_UART1 34
+#define AWIN_IRQ_UART2 35
+#define AWIN_IRQ_UART3 36
+#define AWIN_IRQ_IR0 37
+#define AWIN_IRQ_IR1 38
+#define AWIN_IRQ_TWI0 39
+#define AWIN_IRQ_TWI1 40
+#define AWIN_IRQ_TWI2 41
+#define AWIN_IRQ_SPI0 42
+#define AWIN_IRQ_SPI1 43
+#define AWIN_IRQ_SPI2 44
+#define AWIN_IRQ_SPDIF 45
+#define AWIN_IRQ_AC97 46
+#define AWIN_IRQ_TS 47
+#define AWIN_IRQ_IIS0 48
+#define AWIN_IRQ_UART4 49
+#define AWIN_IRQ_UART5 50
+#define AWIN_IRQ_UART6 51
+#define AWIN_IRQ_UART7 52
+#define AWIN_IRQ_KEYPAD 53
+#define AWIN_IRQ_TMR0 54
+#define AWIN_IRQ_TMR1 55
+#define AWIN_IRQ_TMR2 56 /* WatchDog */
+#define AWIN_IRQ_TMR3 57
+#define AWIN_IRQ_CAN 58
+#define AWIN_IRQ_DMA 59
+#define AWIN_IRQ_PIO 60
+#define AWIN_IRQ_TP 61
+#define AWIN_IRQ_ADDC 62
+#define AWIN_IRQ_LRADC 63
+#define AWIN_IRQ_SDMMC0 64
+#define AWIN_IRQ_SDMMC1 65
+#define AWIN_IRQ_SDMMC2 66
+#define AWIN_IRQ_SDMMC3 67
+#define AWIN_IRQ_MS 68
+#define AWIN_IRQ_NAND 69
+#define AWIN_IRQ_USB0 70
+#define AWIN_IRQ_USB1 71
+#define AWIN_IRQ_USB2 72
+#define AWIN_IRQ_SCR 73
+#define AWIN_IRQ_CSI0 74
+#define AWIN_IRQ_CSI1 75
+#define AWIN_IRQ_LCD0 76
+#define AWIN_IRQ_LCD1 77
+#define AWIN_IRQ_MP 78
+#define AWIN_IRQ_DE_XE0 79
+#define AWIN_IRQ_DE_XE1 80
+#define AWIN_IRQ_PMU 81
+#define AWIN_IRQ_SPI3 82
+#define AWIN_IRQ_TZASC 83
+#define AWIN_IRQ_PATA 84
+#define AWIN_IRQ_VE 85
+#define AWIN_IRQ_SS 86
+#define AWIN_IRQ_EMAC 87
+#define AWIN_IRQ_SATA 88
+#define AWIN_IRQ__RSVD89 89
+#define AWIN_IRQ_HDMI0 90
+#define AWIN_IRQ_TVE 91
+#define AWIN_IRQ_ACE 92
+#define AWIN_IRQ_TVD 93
+#define AWIN_IRQ_PS2_0 94
+#define AWIN_IRQ_PS2_1 95
+#define AWIN_IRQ_USB3 96
+#define AWIN_IRQ_USB4 97
+#define AWIN_IRQ_PERFM 98
+#define AWIN_IRQ_TMR4 99
+#define AWIN_IRQ_TMR5 100
+#define AWIN_IRQ_GPU_GP 101
+#define AWIN_IRQ_GPU_GPMMU 102
+#define AWIN_IRQ_GPU_PP0 103
+#define AWIN_IRQ_GPU_PPMMU0 104
+#define AWIN_IRQ_GPU_PMU 105
+#define AWIN_IRQ_GPU_PP1 106
+#define AWIN_IRQ_GPU_PPMMU1 107
+#define AWIN_IRQ_GPU_RSV0 108
+#define AWIN_IRQ_GPU_RSV1 109
+#define AWIN_IRQ_GPU_RSV2 110
+#define AWIN_IRQ_GPU_RSV3 111
+#define AWIN_IRQ_GPU_RSV4 112
+#define AWIN_IRQ_HSTMR0 113
+#define AWIN_IRQ_HSTMR1 114
+#define AWIN_IRQ_HSTMR2 115
+#define AWIN_IRQ_HSTMR3 116
+#define AWIN_IRQ_GMAC 117
+#define AWIN_IRQ_HDMI1 118
+#define AWIN_IRQ_IIS1 119
+#define AWIN_IRQ_TWI3 120
+#define AWIN_IRQ_TWI4 121
+#define AWIN_IRQ_IIS2 122
+
+#endif /* _ARM_ALLWINNER_AWIN_INTR_H_ */
diff -r 7ae4b7bc6882 -r 40d88179dbbf sys/arch/arm/allwinner/awin_reg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Tue Sep 03 18:02:26 2013 +0000
@@ -0,0 +1,398 @@
+/* $NetBSD */
+/*-
+ * Copyright (c) 2013 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_ALLWINNER_AWIN_REG_H
+#define _ARM_ALLWINNER_AWIN_REG_H
+
+#define AWIN_CPUBIST_PBASE 0x3f501000
+#define AWIN_CPUBIST_SIZE 0x00001000
+#define AWIN_SRAM_PBASE 0x00000000
+#define AWIN_SRAM_SIZE 0x00100000 /* round to 1MB */
+#define AWIN_SRAMA1_PBASE 0x00000000
+#define AWIN_SRAMA1_SIZE 0x00004000
+#define AWIN_SRAMA2_PBASE 0x00004000
+#define AWIN_SRAMA2_SIZE 0x00004000
+#define AWIN_SRAMA3_PBASE 0x00008000
+#define AWIN_SRAMA3_SIZE 0x00003400
+#define AWIN_SRAMA4_PBASE 0x0000b400
+#define AWIN_SRAMA4_SIZE 0x00000c00
+#define AWIN_SRAMD_PBASE 0x00010000
+#define AWIN_SRAMD_SIZE 0x00001000
+#define AWIN_SRAMB_PBASE 0x00020000 /* Secure */
+#define AWIN_SRAMB_SIZE 0x00010000 /* Secure */
+
+#define AWIN_CORE_PBASE 0x01c00000
+#define AWIN_CORE_SIZE 0x00300000
+#define AWIN_SRAM_OFFSET 0x00000000
+#define AWIN_DRAM_OFFSET 0x00001000
+#define AWIN_DMA_OFFSET 0x00002000
+#define AWIN_NFC_OFFSET 0x00003000
+#define AWIN_TS_OFFSET 0x00004000
+#define AWIN_SPI0_OFFSET 0x00005000
+#define AWIN_SPI1_OFFSET 0x00006000
+#define AWIN_MS_OFFSET 0x00007000
+#define AWIN_TVD_OFFSET 0x00008000
+#define AWIN_CSI0_OFFSET 0x00009000
+#define AWIN_TVE0_OFFSET 0x0000a000
+#define AWIN_EMAC_OFFSET 0x0000b000
+#define AWIN_LCD0_OFFSET 0x0000c000
+#define AWIN_LCD1_OFFSET 0x0000d000
+#define AWIN_VE_OFFSET 0x0000e000
+#define AWIN_SDMMC0_OFFSET 0x0000f000
+#define AWIN_SDMMC1_OFFSET 0x00010000
+#define AWIN_SDMMC2_OFFSET 0x00011000
+#define AWIN_SDMMC3_OFFSET 0x00012000
+#define AWIN_USB0_OFFSET 0x00013000
+#define AWIN_USB1_OFFSET 0x00014000
+#define AWIN_SS_OFFSET 0x00015000
+#define AWIN_HDMI_OFFSET 0x00016000
+#define AWIN_SPI2_OFFSET 0x00017000
+#define AWIN_SATA_OFFSET 0x00018000 /* A20 */
+#define AWIN_PATA_OFFSET 0x00019000 /* A10 */
+#define AWIN_ACE_OFFSET 0x0001a000
+#define AWIN_TVE1_OFFSET 0x0001b000
+#define AWIN_USB2_OFFSET 0x0001c000
+#define AWIN_CSI1_OFFSET 0x0001d000
+#define AWIN_TZASC_OFFSET 0x0001e000 /* A10 */
+#define AWIN_SPI3_OFFSET 0x0001f000
+#define AWIN_CCM_OFFSET 0x00020000
+#define AWIN_INTC_OFFSET 0x00020400
+#define AWIN_PIO_OFFSET 0x00020800
+#define AWIN_TIMER_OFFSET 0x00020c00
+#define AWIN_SPDIF_OFFSET 0x00021000 /* A20 */
+#define AWIN_AC97_OFFSET 0x00021400
+#define AWIN_IR0_OFFSET 0x00021800
+#define AWIN_IR1_OFFSET 0x00021c00
+#define AWIN_IIS0_OFFSET 0x00022000
+#define AWIN_IIS1_OFFSET 0x00022400
+#define AWIN_LRADC_OFFSET 0x00022800
+#define AWIN_ADDA_OFFSET 0x00022c00
+#define AWIN_KEYPAD_OFFSET 0x00023000
+#define AWIN_TZPC_OFFSET 0x00023400 /* A10 */
+#define AWIN_SID_OFFSET 0x00023800
+#define AWIN_SJTAG_OFFSET 0x00023c00
+#define AWIN__RSVD3_OFFSET 0x00024000
+#define AWIN_IIS2_OFFSET 0x00024400
+#define AWIN__RSVD4_OFFSET 0x00024800
+#define AWIN__RSVD5_OFFSET 0x00024c00
+#define AWIN_TP_OFFSET 0x00025000
+#define AWIN_PMU_OFFSET 0x00025400
+#define AWIN__RSVD6_OFFSET 0x00025800
+#define AWIN_CPUCNF_OFFSET 0x00025c00
+#define AWIN__RSVD7_OFFSET 0x00026000
+#define AWIN__RSVD8_OFFSET 0x00026400
+#define AWIN__RSVD9_OFFSET 0x00026800
+#define AWIN__RSVD10_OFFSET 0x00026c00
+#define AWIN__RSVD11_OFFSET 0x00027000
+#define AWIN__RSVD12_OFFSET 0x00027400
+#define AWIN__RSVD13_OFFSET 0x00027800
+#define AWIN__RSVD14_OFFSET 0x00027c00
+#define AWIN_UART_FREQ (24*1000*1000) /* 24MHz */
+#define AWIN_UART_SIZE 0x00000100
+#define AWIN_UART0_OFFSET 0x00028000
+#define AWIN_UART1_OFFSET 0x00028400
+#define AWIN_UART2_OFFSET 0x00028800
+#define AWIN_UART3_OFFSET 0x00028c00
+#define AWIN_UART4_OFFSET 0x00029000
+#define AWIN_UART5_OFFSET 0x00029400
+#define AWIN_UART6_OFFSET 0x00029800
+#define AWIN_UART7_OFFSET 0x00029c00
+#define AWIN_PS20_OFFSET 0x0002a000
+#define AWIN_PS21_OFFSET 0x0002a400
+#define AWIN__RSVD15_OFFSET 0x0002a800
+#define AWIN_TWI0_OFFSET 0x0002ac00
+#define AWIN_TWI1_OFFSET 0x0002b000
+#define AWIN_TWI2_OFFSET 0x0002b400
+#define AWIN_TWI3_OFFSET 0x0002b800
+#define AWIN_CAN_OFFSET 0x0002bc00
+#define AWIN_TWI4_OFFSET 0x0002c000 /* A20 */
+#define AWIN_SCR_OFFSET 0x0002c400
+#define AWIN_GPS_OFFSET 0x00030000
+#define AWIN_MALI400_OFFSET 0x00040000
+#define AWIN_GMAC_OFFSET 0x00050000
+#define AWIN_HSTMR_OFFSET 0x00060000 /* A20 */
+#define AWIN_GIC_OFFSET 0x00080000 /* A20 */
+#define AWIN_HDMI1_OFFSET 0x000E0000 /* A20 */
+#define AWIN_SRAMC_OFFSET 0x00100000
+#define AWIN_DE_FE0_OFFSET 0x00200000
+#define AWIN_DE_FE1_OFFSET 0x00220000
+#define AWIN_DE_BE1_OFFSET 0x00240000
+#define AWIN_DE_BE0_OFFSET 0x00260000
+#define AWIN_MP_OFFSET 0x00280000
+#define AWIN_AVG_OFFSET 0x002A0000
+#define AWIN_SDRAM_PBASE 0x40000000
+
+/* A10/A20 DRAM Controller */
+#define AWIN_DRAM_CCR_REG 0x0000
+#define AWIN_DRAM_DCR_REG 0x0004
+#define AWIN_DRAM_IOCR_REG 0x0008
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