[src/trunk]: src/sys/arch/arm/nvidia Get DC clock parent from devicetree

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/8af1e95735b9
branches:  trunk
changeset: 823205:8af1e95735b9
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun Apr 16 12:22:18 2017 +0000

description:
Get DC clock parent from devicetree

diffstat:

 sys/arch/arm/nvidia/tegra_drm_mode.c |  15 +++++----------
 1 files changed, 5 insertions(+), 10 deletions(-)

diffs (50 lines):

diff -r c41d95e4807d -r 8af1e95735b9 sys/arch/arm/nvidia/tegra_drm_mode.c
--- a/sys/arch/arm/nvidia/tegra_drm_mode.c      Sun Apr 16 12:03:25 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra_drm_mode.c      Sun Apr 16 12:22:18 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_drm_mode.c,v 1.12 2015/12/23 11:58:10 jmcneill Exp $ */
+/* $NetBSD: tegra_drm_mode.c,v 1.13 2017/04/16 12:22:18 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_drm_mode.c,v 1.12 2015/12/23 11:58:10 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_drm_mode.c,v 1.13 2017/04/16 12:22:18 jmcneill Exp $");
 
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
@@ -284,7 +284,6 @@
 {
        struct tegra_drm_softc * const sc = tegra_drm_private(ddev);
        struct tegra_crtc *crtc;
-       struct clk *clk_parent;
        bus_addr_t offset;
        bus_size_t size;
        u_int intr;
@@ -346,12 +345,8 @@
        tegra_pmc_remove_clamping(pmc_partid);
 
        /* Set parent clock */
-       clk_parent = clk_get("pll_d2_out0");
-       if (clk_parent == NULL) {
-               DRM_ERROR("couldn't find pll_d2_out0\n");
-               return -EIO;
-       }
-       error = clk_set_parent(sc->sc_clk_dc[index], clk_parent);
+       error = clk_set_parent(sc->sc_clk_dc[index],
+           sc->sc_clk_dc_parent[index]);
        if (error) {
                DRM_ERROR("failed to set crtc %d clock parent: %d\n",
                    index, error);
@@ -368,7 +363,7 @@
        /* Leave reset */
        fdtbus_reset_deassert(sc->sc_rst_dc[index]);
 
-       crtc->clk_parent = clk_parent;
+       crtc->clk_parent = sc->sc_clk_dc_parent[index];
 
        DC_WRITE(crtc, DC_CMD_INT_ENABLE_REG, DC_CMD_INT_V_BLANK);