[src/trunk]: src/sys/arch/mips/cavium Fixup IPI interrupt delivery and splsch...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e38991370d1d
branches:  trunk
changeset: 818777:e38991370d1d
user:      skrll <skrll%NetBSD.org@localhost>
date:      Mon Oct 31 12:27:22 2016 +0000

description:
Fixup IPI interrupt delivery and splsched mask so that
sys/uvm/pmap/pmap_tlb.c

    541         KASSERTMSG(ci->ci_cpl >= IPL_SCHED,
    542             "%s: cpl (%d) < IPL_SCHED (%d)",
    543             __func__, ci->ci_cpl, IPL_SCHED);

doesn't fire.

diffstat:

 sys/arch/mips/cavium/octeon_intr.c |  8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diffs (36 lines):

diff -r cb38ddab5c16 -r e38991370d1d sys/arch/mips/cavium/octeon_intr.c
--- a/sys/arch/mips/cavium/octeon_intr.c        Mon Oct 31 12:18:10 2016 +0000
+++ b/sys/arch/mips/cavium/octeon_intr.c        Mon Oct 31 12:27:22 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: octeon_intr.c,v 1.7 2016/08/20 06:31:15 skrll Exp $    */
+/*     $NetBSD: octeon_intr.c,v 1.8 2016/10/31 12:27:22 skrll Exp $    */
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
  * All rights reserved.
@@ -45,7 +45,7 @@
 #define __INTR_PRIVATE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.7 2016/08/20 06:31:15 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.8 2016/10/31 12:27:22 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/cpu.h>
@@ -74,7 +74,7 @@
        [IPL_SOFTNET] =         MIPS_SOFT_INT_MASK,
        [IPL_VM] =              MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0,
        [IPL_SCHED] =           MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
-                                   | MIPS_INT_MASK_5,
+                                   | MIPS_INT_MASK_1 | MIPS_INT_MASK_5,
        [IPL_DDB] =             MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0
                                    | MIPS_INT_MASK_1 | MIPS_INT_MASK_5,
        [IPL_HIGH] =            MIPS_INT_MASK,
@@ -326,7 +326,7 @@
 
 #ifdef MULTIPROCESSOR
        // Enable the IPIs
-       cpu->cpu_int0_enable0 |= __BIT(_CIU_INT_MBOX_15_0_SHIFT);
+       cpu->cpu_int1_enable0 |= __BIT(_CIU_INT_MBOX_15_0_SHIFT);
        cpu->cpu_int2_enable0 |= __BIT(_CIU_INT_MBOX_31_16_SHIFT);
 #endif