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[src/trunk]: src/sys/arch Add wdog support. Use wdog to do reset (works for ...
details: https://anonhg.NetBSD.org/src/rev/7763209660c4
branches: trunk
changeset: 789713:7763209660c4
user: matt <matt%NetBSD.org@localhost>
date: Wed Sep 04 17:45:40 2013 +0000
description:
Add wdog support. Use wdog to do reset (works for both A10 & A20).
diffstat:
sys/arch/arm/allwinner/awin_board.c | 11 +--
sys/arch/arm/allwinner/awin_reg.h | 136 ++++++++++++++++++++++++++++++++++
sys/arch/arm/allwinner/awin_var.h | 5 +-
sys/arch/arm/allwinner/awin_wdt.c | 135 +++++++++++++++++++++++++++++++--
sys/arch/arm/allwinner/files.awin | 7 +-
sys/arch/evbarm/cubie/cubie_machdep.c | 22 +----
6 files changed, 271 insertions(+), 45 deletions(-)
diffs (truncated from 483 to 300 lines):
diff -r c17fd208a7bf -r 7763209660c4 sys/arch/arm/allwinner/awin_board.c
--- a/sys/arch/arm/allwinner/awin_board.c Wed Sep 04 17:39:01 2013 +0000
+++ b/sys/arch/arm/allwinner/awin_board.c Wed Sep 04 17:45:40 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_board.c,v 1.1 2013/09/04 02:39:01 matt Exp $ */
+/* $NetBSD: awin_board.c,v 1.2 2013/09/04 17:45:40 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.1 2013/09/04 02:39:01 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.2 2013/09/04 17:45:40 matt Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -170,10 +170,3 @@
#endif
return memsize;
}
-
-void
-awin_reset(void)
-{
- bus_space_write_4(&awin_bs_tag, awin_core_bsh,
- AWIN_CPUCNF_OFFSET + AWIN_CPU0_RST_CTRL_REG, AWIN_CPU_RESET);
-}
diff -r c17fd208a7bf -r 7763209660c4 sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Wed Sep 04 17:39:01 2013 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Wed Sep 04 17:45:40 2013 +0000
@@ -232,6 +232,49 @@
#define AWIN_OSC24M_CFG_REG 0x0050
#define AWIN_CPU_AHB_APB0_CFG_REG 0x0054
#define AWIN_APB1_CLK_DIV_REG 0x0058
+#define AWIN_AXI_GATING_REG 0x005c
+#define AWIN_AHB_GATING0_REG 0x0060
+#define AWIN_AHB_GATING1_REG 0x0064
+#define AWIN_APB0_GATING_REG 0x0068
+#define AWIN_APB1_GATING_REG 0x006c
+#define AWIN_NAND_SCLK_CFG_REG 0x0080
+#define AWIN_SD0_CLK_REG 0x0088
+#define AWIN_SD1_CLK_REG 0x008c
+#define AWIN_SD2_CLK_REG 0x0090
+#define AWIN_SD3_CLK_REG 0x0094
+#define AWIN_TS_CLK_REG 0x0098
+#define AWIN_SS_CLK_REG 0x009c
+#define AWIN_SPI0_CLK_REG 0x00a0
+#define AWIN_SPI1_CLK_REG 0x00a4
+#define AWIN_SPI2_CLK_REG 0x00a8
+#define AWIN_IR0_CLK_REG 0x00b9
+#define AWIN_IR1_CLK_REG 0x00b4
+#define AWIN_IIS_CLK_REG 0x00b8
+#define AWIN_AC97_CLK_REG 0x00bc
+#define AWIN_KEYPAD_CLK_REG 0x00c4
+#define AWIN_USB_CLK_REG 0x00cc
+#define AWIN_SPI3_CLK_REG 0x00d4
+#define AWIN_DRAM_CLK_REG 0x0100
+#define AWIN_BE0_SCLK_CFG_REG 0x0100
+#define AWIN_BE0_SCLK_CFG_REG 0x0100
+#define AWIN_FE0_CLK_REG 0x0100
+#define AWIN_FE1_CLK_REG 0x0110
+#define AWIN_MP_CLK_REG 0x0114
+#define AWIN_LCD0_CH0_CLK_REG 0x0118
+#define AWIN_LCD1_CH0_CLK_REG 0x011c
+#define AWIN_CSI_ISP_CLK_REG 0x0120
+#define AWIN_TVD_CLK_REG 0x0128
+#define AWIN_LCD0_CH1_CLK_REG 0x012c
+#define AWIN_LCD1_CH1_CLK_REG 0x0130
+#define AWIN_CSI0_CLK_REG 0x0134
+#define AWIN_CSI1_CLK_REG 0x0138
+#define AWIN_VE_CLK_REG 0x013c
+#define AWIN_AUDIO_CODEC_CLK_REG 0x0140
+#define AWIN_AVS_CLK_REG 0x0144
+#define AWIN_ACE_CLK_REG 0x0148
+#define AWIN_LVDS_CLK_REG 0x014c
+#define AWIN_HDMI_CLK_REG 0x0150
+#define AWIN_MALI400_CLK_REG 0x0154
#define AWIN_OSC24M_CFG_ENABLE __BIT(0)
@@ -249,6 +292,82 @@
#define AWIN_CPU_CLK_SRC_SEL_200MHZ 3
#define AWIN_APB0_CLK_RATIO __BITS(9,8)
+#define AWIN_AHB_GATING0_NC25 __BIT(25)
+#define AWIN_AHB_GATING0_PATA __BIT(24)
+#define AWIN_AHB_GATING0_SPI3 __BIT(23)
+#define AWIN_AHB_GATING0_SPI2 __BIT(22)
+#define AWIN_AHB_GATING0_SPI1 __BIT(21)
+#define AWIN_AHB_GATING0_SPI0 __BIT(20)
+#define AWIN_AHB_GATING0_TS __BIT(18)
+#define AWIN_AHB_GATING0_EMAC __BIT(17)
+#define AWIN_AHB_GATING0_ACE __BIT(16)
+#define AWIN_AHB_GATING0_SDRAM __BIT(14)
+#define AWIN_AHB_GATING0_NAND __BIT(13)
+#define AWIN_AHB_GATING0_NC12 __BIT(12)
+#define AWIN_AHB_GATING0_SDMMC3 __BIT(11)
+#define AWIN_AHB_GATING0_SDMMC2 __BIT(10)
+#define AWIN_AHB_GATING0_SDMMC1 __BIT(9)
+#define AWIN_AHB_GATING0_SDMMC0 __BIT(8)
+#define AWIN_AHB_GATING0_BIST __BIT(7)
+#define AWIN_AHB_GATING0_DMA __BIT(6)
+#define AWIN_AHB_GATING0_SS __BIT(5)
+#define AWIN_AHB_GATING0_USB_EHCI1 __BIT(3)
+#define AWIN_AHB_GATING0_USB_EHCI0 __BIT(1)
+#define AWIN_AHB_GATING0_USB0 __BIT(0)
+
+#define AWIN_AHB_GATING1_MALI400 __BIT(20)
+#define AWIN_AHB_GATING1_MP __BIT(18)
+#define AWIN_AHB_GATING1_DE_FE1 __BIT(15)
+#define AWIN_AHB_GATING1_DE_FE0 __BIT(14)
+#define AWIN_AHB_GATING1_DE_BE1 __BIT(13)
+#define AWIN_AHB_GATING1_DE_BE0 __BIT(12)
+#define AWIN_AHB_GATING1_HDMI __BIT(11)
+#define AWIN_AHB_GATING1_CSI1 __BIT(9)
+#define AWIN_AHB_GATING1_CSI0 __BIT(8)
+#define AWIN_AHB_GATING1_LCD1 __BIT(5)
+#define AWIN_AHB_GATING1_LCD0 __BIT(4)
+#define AWIN_AHB_GATING1_TVE1 __BIT(3)
+#define AWIN_AHB_GATING1_TVE0 __BIT(2)
+#define AWIN_AHB_GATING1_TVD __BIT(1)
+#define AWIN_AHB_GATING1_VE __BIT(0)
+
+#define AWIN_CLK_ENABLE __BIT(31)
+#define AWIN_CLK_SRC_SEL __BITS(25,24)
+#define AWIN_CLK_SRC_SEL_OSC24M 0
+#define AWIN_CLK_SRC_SEL_PLL6 1
+#define AWIN_CLK_SRC_SEL_PLL5 2
+#define AWIN_CLK_DIV_RATIO_N __BITS(17,16)
+#define AWIN_CLK_DIV_RATIO_M __BITS(3,0)
+
+/* SDMMC definitions */
+#define AWIN_SDMMC_GCTRL_REG 0x0000
+#define AWIN_SDMMC_CLKCR_REG 0x0004
+#define AWIN_SDMMC_TIMEOUT_REG 0x0008
+#define AWIN_SDMMC_WIDTH_REG 0x000c
+#define AWIN_SDMMC_BLKSZ_REG 0x0010
+#define AWIN_SDMMC_BYTECNT_REG 0x0014
+#define AWIN_SDMMC_CMD_REG 0x0018
+#define AWIN_SDMMC_ARG_REG 0x001c
+#define AWIN_SDMMC_RESP0_REG 0x0020
+#define AWIN_SDMMC_RESP1_REG 0x0024
+#define AWIN_SDMMC_RESP2_REG 0x0028
+#define AWIN_SDMMC_RESP3_REG 0x002c
+#define AWIN_SDMMC_IMASK_REG 0x0030
+#define AWIN_SDMMC_MINT_REG 0x0034
+#define AWIN_SDMMC_RINT_REG 0x0038
+#define AWIN_SDMMC_STATUS_REG 0x003c
+#define AWIN_SDMMC_FTRGLVL_REG 0x0040
+#define AWIN_SDMMC_FUNCSEL_REG 0x0044
+#define AWIN_SDMMC_CBCR_REG 0x0048
+#define AWIN_SDMMC_BBCR_REG 0x004c
+#define AWIN_SDMMC_DMAC_REG 0x0080
+#define AWIN_SDMMC_DLBA_REG 0x0084
+#define AWIN_SDMMC_IDST_REG 0x0088
+#define AWIN_SDMMC_IDIE_REG 0x008c
+#define AWIN_SDMMC_CHDA_REG 0x0090
+#define AWIN_SDMMC_CBDA_REG 0x0094
+#define AWIN_SDMMC_FIFO_REG 0x0100
+
/* USB device offsets */
#define AWIN_EHCI_OFFSET 0x0000
#define AWIN_EHCI_SIZE 0x0400
@@ -332,6 +451,23 @@
#define AWIN_TMR_GP_DATA3_REG 0x012C
#define AWIN_CPU_CFG_REG 0x0140
+#define AWIN_WDOG_CTRL_RSTART __BIT(1)
+#define AWIN_WDOG_MODE_INTV __BITS(6,3)
+#define AWIN_WDOG_MODE_INTV_HALFSEC 0
+#define AWIN_WDOG_MODE_INTV_1SEC 1
+#define AWIN_WDOG_MODE_INTV_2SEC 2
+#define AWIN_WDOG_MODE_INTV_3SEC 3
+#define AWIN_WDOG_MODE_INTV_4SEC 4
+#define AWIN_WDOG_MODE_INTV_5SEC 5
+#define AWIN_WDOG_MODE_INTV_6SEC 6
+#define AWIN_WDOG_MODE_INTV_8SEC 7
+#define AWIN_WDOG_MODE_INTV_10SEC 8
+#define AWIN_WDOG_MODE_INTV_12SEC 9
+#define AWIN_WDOG_MODE_INTV_14SEC 10
+#define AWIN_WDOG_MODE_INTV_16SEC 11
+#define AWIN_WDOG_MODE_RST_EN __BIT(1)
+#define AWIN_WDOG_MODE_EN __BIT(0)
+
#define AWIN_TWI_ADDR_REG 0x0000
#define AWIN_TWI_XADDR_REG 0x0004
#define AWIN_TWI_DATA_REG 0x0008
diff -r c17fd208a7bf -r 7763209660c4 sys/arch/arm/allwinner/awin_var.h
--- a/sys/arch/arm/allwinner/awin_var.h Wed Sep 04 17:39:01 2013 +0000
+++ b/sys/arch/arm/allwinner/awin_var.h Wed Sep 04 17:45:40 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_var.h,v 1.2 2013/09/04 02:39:01 matt Exp $ */
+/* $NetBSD: awin_var.h,v 1.3 2013/09/04 17:45:40 matt Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -63,8 +63,7 @@
psize_t awin_memprobe(void);
void awin_bootstrap(vaddr_t, vaddr_t);
-void awin_reset(void);
-bool awin_wdt_enable(bool);
+void awin_wdog_reset(void);
#endif /* _ARM_ALLWINNER_AWIN_VAR_H_ */
diff -r c17fd208a7bf -r 7763209660c4 sys/arch/arm/allwinner/awin_wdt.c
--- a/sys/arch/arm/allwinner/awin_wdt.c Wed Sep 04 17:39:01 2013 +0000
+++ b/sys/arch/arm/allwinner/awin_wdt.c Wed Sep 04 17:45:40 2013 +0000
@@ -28,30 +28,114 @@
*/
#include "locators.h"
+#include "opt_allwinner.h"
+#include "awin_wdt.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_wdt.c,v 1.1 2013/09/04 02:39:01 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_wdt.c,v 1.2 2013/09/04 17:45:40 matt Exp $");
#include <sys/bus.h>
#include <sys/device.h>
#include <sys/intr.h>
#include <sys/systm.h>
+#include <sys/proc.h>
+#include <sys/wdog.h>
+
+#include <dev/sysmon/sysmonvar.h>
+
+#include <arm/locore.h>
#include <arm/allwinner/awin_reg.h>
#include <arm/allwinner/awin_var.h>
+#if NAWIN_WDT > 0
static int awin_wdt_match(device_t, cfdata_t, void *);
static void awin_wdt_attach(device_t, device_t, void *);
-struct awin_wdt_softc {
+#ifndef AWIN_WDT_PERIOD_DEFAULT
+#define AWIN_WDT_PERIOD_DEFAULT 10
+#endif
+
+static const uint8_t period_map[] = {
+ [0] = __SHIFTIN(AWIN_WDOG_MODE_INTV_1SEC, AWIN_WDOG_MODE_INTV),
+ [1] = __SHIFTIN(AWIN_WDOG_MODE_INTV_1SEC, AWIN_WDOG_MODE_INTV),
+ [2] = __SHIFTIN(AWIN_WDOG_MODE_INTV_2SEC, AWIN_WDOG_MODE_INTV),
+ [3] = __SHIFTIN(AWIN_WDOG_MODE_INTV_3SEC, AWIN_WDOG_MODE_INTV),
+ [4] = __SHIFTIN(AWIN_WDOG_MODE_INTV_4SEC, AWIN_WDOG_MODE_INTV),
+ [5] = __SHIFTIN(AWIN_WDOG_MODE_INTV_5SEC, AWIN_WDOG_MODE_INTV),
+ [6] = __SHIFTIN(AWIN_WDOG_MODE_INTV_6SEC, AWIN_WDOG_MODE_INTV),
+ [7] = __SHIFTIN(AWIN_WDOG_MODE_INTV_8SEC, AWIN_WDOG_MODE_INTV),
+ [8] = __SHIFTIN(AWIN_WDOG_MODE_INTV_8SEC, AWIN_WDOG_MODE_INTV),
+ [9] = __SHIFTIN(AWIN_WDOG_MODE_INTV_10SEC, AWIN_WDOG_MODE_INTV),
+ [10] = __SHIFTIN(AWIN_WDOG_MODE_INTV_10SEC, AWIN_WDOG_MODE_INTV),
+ [11] = __SHIFTIN(AWIN_WDOG_MODE_INTV_12SEC, AWIN_WDOG_MODE_INTV),
+ [12] = __SHIFTIN(AWIN_WDOG_MODE_INTV_12SEC, AWIN_WDOG_MODE_INTV),
+ [13] = __SHIFTIN(AWIN_WDOG_MODE_INTV_14SEC, AWIN_WDOG_MODE_INTV),
+ [14] = __SHIFTIN(AWIN_WDOG_MODE_INTV_14SEC, AWIN_WDOG_MODE_INTV),
+ [15] = __SHIFTIN(AWIN_WDOG_MODE_INTV_16SEC, AWIN_WDOG_MODE_INTV),
+ [16] = __SHIFTIN(AWIN_WDOG_MODE_INTV_16SEC, AWIN_WDOG_MODE_INTV),
+};
+
+static struct awin_wdt_softc {
device_t sc_dev;
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh;
- bus_dma_tag_t sc_dmat;
+ struct sysmon_wdog sc_smw;
+ u_int sc_wdog_period;
+ bool sc_wdog_armed;
+ uint32_t sc_wdog_mode;
+} awin_wdt_sc = {
+ .sc_bst = &awin_bs_tag,
+ .sc_wdog_period = AWIN_WDT_PERIOD_DEFAULT,
};
-CFATTACH_DECL_NEW(awin_wdt, sizeof(struct awin_wdt_softc),
+static int
+awin_wdt_tickle(struct sysmon_wdog *smw)
+{
+ struct awin_wdt_softc * const sc = smw->smw_cookie;
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_WDOG_CTRL_REG,
+ AWIN_WDOG_CTRL_RSTART);
+ return 0;
+}
+
+static int
+awin_wdt_setmode(struct sysmon_wdog *smw)
+{
+ struct awin_wdt_softc * const sc = smw->smw_cookie;
+
+ if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
+ /*
+ * We can't disarm the watchdog.
+ */
+ return sc->sc_wdog_armed ? EBUSY : 0;
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