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[src/trunk]: src/sys/arch Add initial support for Allwinner H3 SoC.
details: https://anonhg.NetBSD.org/src/rev/ed3d963a2925
branches: trunk
changeset: 825067:ed3d963a2925
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Wed Jun 28 23:51:29 2017 +0000
description:
Add initial support for Allwinner H3 SoC.
diffstat:
sys/arch/arm/sunxi/files.sunxi | 37 +++
sys/arch/arm/sunxi/sun8i_h3_ccu.c | 171 ++++++++++++++++++
sys/arch/arm/sunxi/sun8i_h3_ccu.h | 205 +++++++++++++++++++++
sys/arch/arm/sunxi/sunxi_ccu.c | 338 ++++++++++++++++++++++++++++++++++++
sys/arch/arm/sunxi/sunxi_ccu.h | 168 +++++++++++++++++
sys/arch/arm/sunxi/sunxi_ccu_gate.c | 71 +++++++
sys/arch/arm/sunxi/sunxi_ccu_nm.c | 123 +++++++++++++
sys/arch/arm/sunxi/sunxi_com.c | 178 ++++++++++++++++++
sys/arch/arm/sunxi/sunxi_platform.c | 160 +++++++++++++++++
sys/arch/arm/sunxi/sunxi_platform.h | 38 ++++
sys/arch/evbarm/conf/SUNXI | 109 +++++++++++
sys/arch/evbarm/conf/files.sunxi | 8 +
sys/arch/evbarm/conf/mk.sunxi | 32 +++
sys/arch/evbarm/conf/std.sunxi | 29 +++
sys/arch/evbarm/sunxi/genassym.cf | 38 ++++
sys/arch/evbarm/sunxi/sunxi_start.S | 192 ++++++++++++++++++++
16 files changed, 1897 insertions(+), 0 deletions(-)
diffs (truncated from 1961 to 300 lines):
diff -r 6a494b21fc53 -r ed3d963a2925 sys/arch/arm/sunxi/files.sunxi
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/sunxi/files.sunxi Wed Jun 28 23:51:29 2017 +0000
@@ -0,0 +1,37 @@
+# $NetBSD: files.sunxi,v 1.1 2017/06/28 23:51:29 jmcneill Exp $
+#
+# Configuration info for Allwinner sunxi family SoCs
+#
+#
+
+include "arch/arm/pic/files.pic"
+include "arch/arm/cortex/files.cortex"
+
+file arch/arm/arm32/arm32_boot.c
+file arch/arm/arm32/arm32_kvminit.c
+file arch/arm/arm32/arm32_reboot.c
+file arch/arm/arm32/irq_dispatch.S
+file arch/arm/arm32/armv7_generic_space.c
+file arch/arm/arm32/armv7_generic_dma.c
+file arch/arm/arm/bus_space_a4x.S
+
+file arch/arm/sunxi/sunxi_platform.c soc_sunxi
+
+# CCU
+define sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_gate.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_nm.c sunxi_ccu
+
+device sun8ih3ccu: sunxi_ccu
+attach sun8ih3ccu at fdt with sunxi_h3_ccu
+file arch/arm/sunxi/sun8i_h3_ccu.c sunxi_h3_ccu
+
+# UART
+attach com at fdt with sunxi_com
+file arch/arm/sunxi/sunxi_com.c sunxi_com needs-flag
+
+# SOC parameters
+defflag opt_soc.h SOC_SUNXI
+defflag opt_soc.h SOC_SUN8I: SOC_SUNXI
+defflag opt_soc.h SOC_SUN8I_H3: SOC_SUN8I
diff -r 6a494b21fc53 -r ed3d963a2925 sys/arch/arm/sunxi/sun8i_h3_ccu.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/sunxi/sun8i_h3_ccu.c Wed Jun 28 23:51:29 2017 +0000
@@ -0,0 +1,171 @@
+/* $NetBSD: sun8i_h3_ccu.c,v 1.1 2017/06/28 23:51:29 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * Copyright (c) 2017 Emmanuel Vadot <manu%freebsd.org@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: sun8i_h3_ccu.c,v 1.1 2017/06/28 23:51:29 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/sunxi/sunxi_ccu.h>
+#include <arm/sunxi/sun8i_h3_ccu.h>
+
+#define USBPHY_CFG_REG 0x0cc
+#define MBUS_RST_REG 0x0fc
+#define BUS_SOFT_RST_REG0 0x2c0
+#define BUS_SOFT_RST_REG1 0x2c4
+#define BUS_SOFT_RST_REG2 0x2c8
+#define BUS_SOFT_RST_REG3 0x2d0
+#define BUS_SOFT_RST_REG4 0x2d8
+
+#define APB2_CFG_REG 0x058
+#define BUS_CLK_GATING_REG3 0x06c
+
+static int sun8i_h3_ccu_match(device_t, cfdata_t, void *);
+static void sun8i_h3_ccu_attach(device_t, device_t, void *);
+
+static const char * const compatible[] = {
+ "allwinner,sun8i-h3-ccu",
+ NULL
+};
+
+CFATTACH_DECL_NEW(sunxi_h3_ccu, sizeof(struct sunxi_ccu_softc),
+ sun8i_h3_ccu_match, sun8i_h3_ccu_attach, NULL, NULL);
+
+static struct sunxi_ccu_reset sun8i_h3_ccu_resets[] = {
+ SUNXI_CCU_RESET(H3_RST_USB_PHY0, USBPHY_CFG_REG, 0),
+ SUNXI_CCU_RESET(H3_RST_USB_PHY1, USBPHY_CFG_REG, 1),
+ SUNXI_CCU_RESET(H3_RST_USB_PHY2, USBPHY_CFG_REG, 2),
+ SUNXI_CCU_RESET(H3_RST_USB_PHY3, USBPHY_CFG_REG, 3),
+
+ SUNXI_CCU_RESET(H3_RST_MBUS, MBUS_RST_REG, 31),
+
+ SUNXI_CCU_RESET(H3_RST_BUS_CE, BUS_SOFT_RST_REG0, 5),
+ SUNXI_CCU_RESET(H3_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6),
+ SUNXI_CCU_RESET(H3_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8),
+ SUNXI_CCU_RESET(H3_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9),
+ SUNXI_CCU_RESET(H3_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10),
+ SUNXI_CCU_RESET(H3_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13),
+ SUNXI_CCU_RESET(H3_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14),
+ SUNXI_CCU_RESET(H3_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17),
+ SUNXI_CCU_RESET(H3_RST_BUS_TS, BUS_SOFT_RST_REG0, 18),
+ SUNXI_CCU_RESET(H3_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19),
+ SUNXI_CCU_RESET(H3_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20),
+ SUNXI_CCU_RESET(H3_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21),
+ SUNXI_CCU_RESET(H3_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23),
+ SUNXI_CCU_RESET(H3_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24),
+ SUNXI_CCU_RESET(H3_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25),
+ SUNXI_CCU_RESET(H3_RST_BUS_EHCI2, BUS_SOFT_RST_REG0, 26),
+ SUNXI_CCU_RESET(H3_RST_BUS_EHCI3, BUS_SOFT_RST_REG0, 27),
+ SUNXI_CCU_RESET(H3_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28),
+ SUNXI_CCU_RESET(H3_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29),
+ SUNXI_CCU_RESET(H3_RST_BUS_OHCI2, BUS_SOFT_RST_REG0, 30),
+ SUNXI_CCU_RESET(H3_RST_BUS_OHCI3, BUS_SOFT_RST_REG0, 31),
+
+ SUNXI_CCU_RESET(H3_RST_BUS_VE, BUS_SOFT_RST_REG1, 0),
+ SUNXI_CCU_RESET(H3_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3),
+ SUNXI_CCU_RESET(H3_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4),
+ SUNXI_CCU_RESET(H3_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5),
+ SUNXI_CCU_RESET(H3_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8),
+ SUNXI_CCU_RESET(H3_RST_BUS_TVE, BUS_SOFT_RST_REG1, 9),
+ SUNXI_CCU_RESET(H3_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10),
+ SUNXI_CCU_RESET(H3_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11),
+ SUNXI_CCU_RESET(H3_RST_BUS_DE, BUS_SOFT_RST_REG1, 12),
+ SUNXI_CCU_RESET(H3_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20),
+ SUNXI_CCU_RESET(H3_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21),
+ SUNXI_CCU_RESET(H3_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22),
+ SUNXI_CCU_RESET(H3_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31),
+
+ SUNXI_CCU_RESET(H3_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2),
+
+ SUNXI_CCU_RESET(H3_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0),
+ SUNXI_CCU_RESET(H3_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1),
+ SUNXI_CCU_RESET(H3_RST_BUS_THS, BUS_SOFT_RST_REG3, 8),
+ SUNXI_CCU_RESET(H3_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12),
+ SUNXI_CCU_RESET(H3_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13),
+ SUNXI_CCU_RESET(H3_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14),
+
+ SUNXI_CCU_RESET(H3_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0),
+ SUNXI_CCU_RESET(H3_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1),
+ SUNXI_CCU_RESET(H3_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2),
+ SUNXI_CCU_RESET(H3_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16),
+ SUNXI_CCU_RESET(H3_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17),
+ SUNXI_CCU_RESET(H3_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18),
+ SUNXI_CCU_RESET(H3_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19),
+ SUNXI_CCU_RESET(H3_RST_BUS_SCR, BUS_SOFT_RST_REG4, 20),
+};
+
+static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" };
+
+static struct sunxi_ccu_clk sun8i_h3_ccu_clks[] = {
+ SUNXI_CCU_NM(H3_CLK_APB2, "apb2", apb2_parents,
+ APB2_CFG_REG, __BITS(17,16), __BITS(4,0), __BITS(25,24),
+ SUNXI_CCU_NM_POWER_OF_TWO),
+
+ SUNXI_CCU_GATE(H3_CLK_BUS_UART0, "bus-uart0", "apb2",
+ BUS_CLK_GATING_REG3, 19),
+};
+
+static int
+sun8i_h3_ccu_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+sun8i_h3_ccu_attach(device_t parent, device_t self, void *aux)
+{
+ struct sunxi_ccu_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+
+ sc->sc_dev = self;
+ sc->sc_phandle = faa->faa_phandle;
+ sc->sc_bst = faa->faa_bst;
+
+ sc->sc_resets = sun8i_h3_ccu_resets;
+ sc->sc_nresets = __arraycount(sun8i_h3_ccu_resets);
+
+ sc->sc_clks = sun8i_h3_ccu_clks;
+ sc->sc_nclks = __arraycount(sun8i_h3_ccu_clks);
+
+ if (sunxi_ccu_attach(sc) != 0)
+ return;
+
+ aprint_naive("\n");
+ aprint_normal(": H3 CCU\n");
+
+ sunxi_ccu_print(sc);
+}
diff -r 6a494b21fc53 -r ed3d963a2925 sys/arch/arm/sunxi/sun8i_h3_ccu.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/sunxi/sun8i_h3_ccu.h Wed Jun 28 23:51:29 2017 +0000
@@ -0,0 +1,205 @@
+/* $NetBSD: sun8i_h3_ccu.h,v 1.1 2017/06/28 23:51:29 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Emmanuel Vadot <manu%freebsd.org@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef __CCU_H3_H__
+#define __CCU_H3_H__
+
+#define H3_RST_USB_PHY0 0
+#define H3_RST_USB_PHY1 1
+#define H3_RST_USB_PHY2 2
+#define H3_RST_USB_PHY3 3
+#define H3_RST_MBUS 4
+#define H3_RST_BUS_CE 5
+#define H3_RST_BUS_DMA 6
+#define H3_RST_BUS_MMC0 7
+#define H3_RST_BUS_MMC1 8
+#define H3_RST_BUS_MMC2 9
+#define H3_RST_BUS_NAND 10
+#define H3_RST_BUS_DRAM 11
+#define H3_RST_BUS_EMAC 12
+#define H3_RST_BUS_TS 13
+#define H3_RST_BUS_HSTIMER 14
+#define H3_RST_BUS_SPI0 15
+#define H3_RST_BUS_SPI1 16
+#define H3_RST_BUS_OTG 17
+#define H3_RST_BUS_EHCI0 18
+#define H3_RST_BUS_EHCI1 19
+#define H3_RST_BUS_EHCI2 20
+#define H3_RST_BUS_EHCI3 21
+#define H3_RST_BUS_OHCI0 22
+#define H3_RST_BUS_OHCI1 23
+#define H3_RST_BUS_OHCI2 24
+#define H3_RST_BUS_OHCI3 25
+#define H3_RST_BUS_VE 26
+#define H3_RST_BUS_TCON0 27
+#define H3_RST_BUS_TCON1 28
+#define H3_RST_BUS_DEINTERLACE 29
+#define H3_RST_BUS_CSI 30
+#define H3_RST_BUS_TVE 31
+#define H3_RST_BUS_HDMI0 32
+#define H3_RST_BUS_HDMI1 33
+#define H3_RST_BUS_DE 34
+#define H3_RST_BUS_GPU 35
+#define H3_RST_BUS_MSGBOX 36
+#define H3_RST_BUS_SPINLOCK 37
+#define H3_RST_BUS_DBG 38
+#define H3_RST_BUS_EPHY 39
+#define H3_RST_BUS_CODEC 40
+#define H3_RST_BUS_SPDIF 41
+#define H3_RST_BUS_THS 42
+#define H3_RST_BUS_I2S0 43
+#define H3_RST_BUS_I2S1 44
+#define H3_RST_BUS_I2S2 45
+#define H3_RST_BUS_I2C0 46
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