[src/trunk]: src/sys/dev/pci The MEHE bit in the CTRL register is not bit 17 ...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/df918d228c6d
branches:  trunk
changeset: 818982:df918d228c6d
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Fri Nov 11 07:31:03 2016 +0000

description:
The MEHE bit in the CTRL register is not bit 17 but 19.

diffstat:

 sys/dev/pci/if_wmreg.h |  4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diffs (18 lines):

diff -r f59a6b2aa7b9 -r df918d228c6d sys/dev/pci/if_wmreg.h
--- a/sys/dev/pci/if_wmreg.h    Thu Nov 10 23:47:23 2016 +0000
+++ b/sys/dev/pci/if_wmreg.h    Fri Nov 11 07:31:03 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_wmreg.h,v 1.89 2016/05/06 08:56:20 msaitoh Exp $    */
+/*     $NetBSD: if_wmreg.h,v 1.90 2016/11/11 07:31:03 msaitoh Exp $    */
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
@@ -237,7 +237,7 @@
 #define        CTRL_SWDPIO_SHIFT       22
 #define        CTRL_SWDPIO_MASK        0x0f
 #define        CTRL_SWDPIO(x)          (1U << (CTRL_SWDPIO_SHIFT + (x)))
-#define CTRL_MEHE      (1U << 17)      /* Memory Error Handling Enable(I217)*/
+#define CTRL_MEHE      (1U << 19)      /* Memory Error Handling Enable(I217)*/
 #define        CTRL_RST        (1U << 26)      /* device reset */
 #define        CTRL_RFCE       (1U << 27)      /* Rx flow control enable */
 #define        CTRL_TFCE       (1U << 28)      /* Tx flow control enable */