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[src/trunk]: src/sys/external/bsd/dwc2/dist Import dwc2 2013-09-25
details: https://anonhg.NetBSD.org/src/rev/5d9e441df1fd
branches: trunk
changeset: 790194:5d9e441df1fd
user: skrll <skrll%NetBSD.org@localhost>
date: Wed Sep 25 05:41:15 2013 +0000
description:
Import dwc2 2013-09-25
diffstat:
sys/external/bsd/dwc2/dist/dwc2_hw.h | 154 ++++++++++++++++------------------
1 files changed, 74 insertions(+), 80 deletions(-)
diffs (271 lines):
diff -r 0b23219d52ee -r 5d9e441df1fd sys/external/bsd/dwc2/dist/dwc2_hw.h
--- a/sys/external/bsd/dwc2/dist/dwc2_hw.h Wed Sep 25 03:28:20 2013 +0000
+++ b/sys/external/bsd/dwc2/dist/dwc2_hw.h Wed Sep 25 05:41:15 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc2_hw.h,v 1.1.1.1 2013/09/05 07:53:13 skrll Exp $ */
+/* $NetBSD: dwc2_hw.h,v 1.1.1.2 2013/09/25 05:41:15 skrll Exp $ */
/*
* hw.h - DesignWare HS OTG Controller hardware definitions
@@ -74,11 +74,11 @@
#define GAHBCFG_DMA_EN (1 << 5)
#define GAHBCFG_HBSTLEN_MASK (0xf << 1)
#define GAHBCFG_HBSTLEN_SHIFT 1
-#define GAHBCFG_HBSTLEN_SINGLE (0 << 1)
-#define GAHBCFG_HBSTLEN_INCR (1 << 1)
-#define GAHBCFG_HBSTLEN_INCR4 (3 << 1)
-#define GAHBCFG_HBSTLEN_INCR8 (5 << 1)
-#define GAHBCFG_HBSTLEN_INCR16 (7 << 1)
+#define GAHBCFG_HBSTLEN_SINGLE 0
+#define GAHBCFG_HBSTLEN_INCR 1
+#define GAHBCFG_HBSTLEN_INCR4 3
+#define GAHBCFG_HBSTLEN_INCR8 5
+#define GAHBCFG_HBSTLEN_INCR16 7
#define GAHBCFG_GLBL_INTR_EN (1 << 0)
#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \
GAHBCFG_NP_TXF_EMP_LVL | \
@@ -171,15 +171,15 @@
#define GRXSTS_FN_SHIFT 25
#define GRXSTS_PKTSTS_MASK (0xf << 17)
#define GRXSTS_PKTSTS_SHIFT 17
-#define GRXSTS_PKTSTS_GLOBALOUTNAK (1 << 17)
-#define GRXSTS_PKTSTS_OUTRX (2 << 17)
-#define GRXSTS_PKTSTS_HCHIN (2 << 17)
-#define GRXSTS_PKTSTS_OUTDONE (3 << 17)
-#define GRXSTS_PKTSTS_HCHIN_XFER_COMP (3 << 17)
-#define GRXSTS_PKTSTS_SETUPDONE (4 << 17)
-#define GRXSTS_PKTSTS_DATATOGGLEERR (5 << 17)
-#define GRXSTS_PKTSTS_SETUPRX (6 << 17)
-#define GRXSTS_PKTSTS_HCHHALTED (7 << 17)
+#define GRXSTS_PKTSTS_GLOBALOUTNAK 1
+#define GRXSTS_PKTSTS_OUTRX 2
+#define GRXSTS_PKTSTS_HCHIN 2
+#define GRXSTS_PKTSTS_OUTDONE 3
+#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
+#define GRXSTS_PKTSTS_SETUPDONE 4
+#define GRXSTS_PKTSTS_DATATOGGLEERR 5
+#define GRXSTS_PKTSTS_SETUPRX 6
+#define GRXSTS_PKTSTS_HCHHALTED 7
#define GRXSTS_HCHNUM_MASK (0xf << 0)
#define GRXSTS_HCHNUM_SHIFT 0
#define GRXSTS_DPID_MASK (0x3 << 15)
@@ -190,16 +190,11 @@
#define GRXSTS_EPNUM_SHIFT 0
#define GRXFSIZ HSOTG_REG(0x024)
+#define GRXFSIZ_DEPTH_MASK (0xffff << 0)
+#define GRXFSIZ_DEPTH_SHIFT 0
#define GNPTXFSIZ HSOTG_REG(0x028)
-#define GNPTXFSIZ_NP_TXF_DEP_MASK (0xffff << 16)
-#define GNPTXFSIZ_NP_TXF_DEP_SHIFT 16
-#define GNPTXFSIZ_NP_TXF_DEP_LIMIT 0xffff
-#define GNPTXFSIZ_NP_TXF_DEP(_x) ((_x) << 16)
-#define GNPTXFSIZ_NP_TXF_ST_ADDR_MASK (0xffff << 0)
-#define GNPTXFSIZ_NP_TXF_ST_ADDR_SHIFT 0
-#define GNPTXFSIZ_NP_TXF_ST_ADDR_LIMIT 0xffff
-#define GNPTXFSIZ_NP_TXF_ST_ADDR(_x) ((_x) << 0)
+/* Use FIFOSIZE_* constants to access this register */
#define GNPTXSTS HSOTG_REG(0x02C)
#define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24)
@@ -250,32 +245,32 @@
#define GHWCFG2_NUM_DEV_EP_SHIFT 10
#define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
#define GHWCFG2_FS_PHY_TYPE_SHIFT 8
-#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED (0 << 8)
-#define GHWCFG2_FS_PHY_TYPE_DEDICATED (1 << 8)
-#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI (2 << 8)
-#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI (3 << 8)
+#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0
+#define GHWCFG2_FS_PHY_TYPE_DEDICATED 1
+#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2
+#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3
#define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
#define GHWCFG2_HS_PHY_TYPE_SHIFT 6
-#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED (0 << 6)
-#define GHWCFG2_HS_PHY_TYPE_UTMI (1 << 6)
-#define GHWCFG2_HS_PHY_TYPE_ULPI (2 << 6)
-#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI (3 << 6)
+#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
+#define GHWCFG2_HS_PHY_TYPE_UTMI 1
+#define GHWCFG2_HS_PHY_TYPE_ULPI 2
+#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
#define GHWCFG2_POINT2POINT (1 << 5)
#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
#define GHWCFG2_ARCHITECTURE_SHIFT 3
-#define GHWCFG2_SLAVE_ONLY_ARCH (0 << 3)
-#define GHWCFG2_EXT_DMA_ARCH (1 << 3)
-#define GHWCFG2_INT_DMA_ARCH (2 << 3)
+#define GHWCFG2_SLAVE_ONLY_ARCH 0
+#define GHWCFG2_EXT_DMA_ARCH 1
+#define GHWCFG2_INT_DMA_ARCH 2
#define GHWCFG2_OP_MODE_MASK (0x7 << 0)
#define GHWCFG2_OP_MODE_SHIFT 0
-#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE (0 << 0)
-#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE (1 << 0)
-#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE (2 << 0)
-#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE (3 << 0)
-#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE (4 << 0)
-#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST (5 << 0)
-#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST (6 << 0)
-#define GHWCFG2_OP_MODE_UNDEFINED (7 << 0)
+#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0
+#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1
+#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2
+#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
+#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
+#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
+#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
+#define GHWCFG2_OP_MODE_UNDEFINED 7
#define GHWCFG3 HSOTG_REG(0x004c)
#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
@@ -309,6 +304,9 @@
#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
+#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
#define GHWCFG4_XHIBER (1 << 7)
#define GHWCFG4_HIBER (1 << 6)
#define GHWCFG4_MIN_AHB_FREQ (1 << 5)
@@ -397,16 +395,12 @@
#define ADPCTL_PRB_DSCHRG_SHIFT 0
#define HPTXFSIZ HSOTG_REG(0x100)
+/* Use FIFOSIZE_* constants to access this register */
#define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
-#define DPTXFSIZN_DP_TXF_SIZE_MASK (0xffff << 16)
-#define DPTXFSIZN_DP_TXF_SIZE_SHIFT 16
-#define DPTXFSIZN_DP_TXF_SIZE_GET(_v) (((_v) >> 16) & 0xffff)
-#define DPTXFSIZN_DP_TXF_SIZE_LIMIT 0xffff
-#define DPTXFSIZN_DP_TXF_SIZE(_x) ((_x) << 16)
-#define DPTXFSIZN_DP_TXF_ST_ADDR_MASK (0xffff << 0)
-#define DPTXFSIZN_DP_TXF_ST_ADDR_SHIFT 0
+/* Use FIFOSIZE_* constants to access this register */
+/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
#define FIFOSIZE_DEPTH_MASK (0xffff << 16)
#define FIFOSIZE_DEPTH_SHIFT 16
#define FIFOSIZE_STARTADDR_MASK (0xffff << 0)
@@ -430,10 +424,10 @@
#define DCFG_NZ_STS_OUT_HSHK (1 << 2)
#define DCFG_DEVSPD_MASK (0x3 << 0)
#define DCFG_DEVSPD_SHIFT 0
-#define DCFG_DEVSPD_HS (0 << 0)
-#define DCFG_DEVSPD_FS (1 << 0)
-#define DCFG_DEVSPD_LS (2 << 0)
-#define DCFG_DEVSPD_FS48 (3 << 0)
+#define DCFG_DEVSPD_HS 0
+#define DCFG_DEVSPD_FS 1
+#define DCFG_DEVSPD_LS 2
+#define DCFG_DEVSPD_FS48 3
#define DCTL HSOTG_REG(0x804)
#define DCTL_PWRONPRGDONE (1 << 11)
@@ -456,10 +450,10 @@
#define DSTS_ERRATICERR (1 << 3)
#define DSTS_ENUMSPD_MASK (0x3 << 1)
#define DSTS_ENUMSPD_SHIFT 1
-#define DSTS_ENUMSPD_HS (0 << 1)
-#define DSTS_ENUMSPD_FS (1 << 1)
-#define DSTS_ENUMSPD_LS (2 << 1)
-#define DSTS_ENUMSPD_FS48 (3 << 1)
+#define DSTS_ENUMSPD_HS 0
+#define DSTS_ENUMSPD_FS 1
+#define DSTS_ENUMSPD_LS 2
+#define DSTS_ENUMSPD_FS48 3
#define DSTS_SUSPSTS (1 << 0)
#define DIEPMSK HSOTG_REG(0x810)
@@ -507,10 +501,10 @@
*/
#define D0EPCTL_MPS_MASK (0x3 << 0)
#define D0EPCTL_MPS_SHIFT 0
-#define D0EPCTL_MPS_64 (0 << 0)
-#define D0EPCTL_MPS_32 (1 << 0)
-#define D0EPCTL_MPS_16 (2 << 0)
-#define D0EPCTL_MPS_8 (3 << 0)
+#define D0EPCTL_MPS_64 0
+#define D0EPCTL_MPS_32 1
+#define D0EPCTL_MPS_16 2
+#define D0EPCTL_MPS_8 3
#define DXEPCTL_EPENA (1 << 31)
#define DXEPCTL_EPDIS (1 << 30)
@@ -528,10 +522,10 @@
#define DXEPCTL_SNP (1 << 20)
#define DXEPCTL_EPTYPE_MASK (0x3 << 18)
#define DXEPCTL_EPTYPE_SHIFT 18
-#define DXEPCTL_EPTYPE_CONTROL (0 << 18)
-#define DXEPCTL_EPTYPE_ISO (1 << 18)
-#define DXEPCTL_EPTYPE_BULK (2 << 18)
-#define DXEPCTL_EPTYPE_INTTERUPT (3 << 18)
+#define DXEPCTL_EPTYPE_CONTROL 0
+#define DXEPCTL_EPTYPE_ISO 1
+#define DXEPCTL_EPTYPE_BULK 2
+#define DXEPCTL_EPTYPE_INTTERUPT 3
#define DXEPCTL_NAKSTS (1 << 17)
#define DXEPCTL_DPID (1 << 16)
#define DXEPCTL_EOFRNUM (1 << 16)
@@ -651,9 +645,9 @@
#define HCFG_FSLSSUPP (1 << 2)
#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
#define HCFG_FSLSPCLKSEL_SHIFT 0
-#define HCFG_FSLSPCLKSEL_30_60_MHZ (0 << 0)
-#define HCFG_FSLSPCLKSEL_48_MHZ (1 << 0)
-#define HCFG_FSLSPCLKSEL_6_MHZ (2 << 0)
+#define HCFG_FSLSPCLKSEL_30_60_MHZ 0
+#define HCFG_FSLSPCLKSEL_48_MHZ 1
+#define HCFG_FSLSPCLKSEL_6_MHZ 2
#define HFIR HSOTG_REG(0x0404)
#define HFIR_FRINT_MASK (0xffff << 0)
@@ -686,9 +680,9 @@
#define HPRT0 HSOTG_REG(0x0440)
#define HPRT0_SPD_MASK (0x3 << 17)
#define HPRT0_SPD_SHIFT 17
-#define HPRT0_SPD_HIGH_SPEED (0 << 17)
-#define HPRT0_SPD_FULL_SPEED (1 << 17)
-#define HPRT0_SPD_LOW_SPEED (2 << 17)
+#define HPRT0_SPD_HIGH_SPEED 0
+#define HPRT0_SPD_FULL_SPEED 1
+#define HPRT0_SPD_LOW_SPEED 2
#define HPRT0_TSTCTL_MASK (0xf << 13)
#define HPRT0_TSTCTL_SHIFT 13
#define HPRT0_PWR (1 << 12)
@@ -726,10 +720,10 @@
#define HCSPLT_COMPSPLT (1 << 16)
#define HCSPLT_XACTPOS_MASK (0x3 << 14)
#define HCSPLT_XACTPOS_SHIFT 14
-#define HCSPLT_XACTPOS_MID (0 << 14)
-#define HCSPLT_XACTPOS_END (1 << 14)
-#define HCSPLT_XACTPOS_BEGIN (2 << 14)
-#define HCSPLT_XACTPOS_ALL (3 << 14)
+#define HCSPLT_XACTPOS_MID 0
+#define HCSPLT_XACTPOS_END 1
+#define HCSPLT_XACTPOS_BEGIN 2
+#define HCSPLT_XACTPOS_ALL 3
#define HCSPLT_HUBADDR_MASK (0x7f << 7)
#define HCSPLT_HUBADDR_SHIFT 7
#define HCSPLT_PRTADDR_MASK (0x7f << 0)
@@ -757,11 +751,11 @@
#define TSIZ_DOPNG (1 << 31)
#define TSIZ_SC_MC_PID_MASK (0x3 << 29)
#define TSIZ_SC_MC_PID_SHIFT 29
-#define TSIZ_SC_MC_PID_DATA0 (0 << 29)
-#define TSIZ_SC_MC_PID_DATA2 (1 << 29)
-#define TSIZ_SC_MC_PID_DATA1 (2 << 29)
-#define TSIZ_SC_MC_PID_MDATA (3 << 29)
-#define TSIZ_SC_MC_PID_SETUP (3 << 29)
+#define TSIZ_SC_MC_PID_DATA0 0
+#define TSIZ_SC_MC_PID_DATA2 1
+#define TSIZ_SC_MC_PID_DATA1 2
+#define TSIZ_SC_MC_PID_MDATA 3
+#define TSIZ_SC_MC_PID_SETUP 3
#define TSIZ_PKTCNT_MASK (0x3ff << 19)
#define TSIZ_PKTCNT_SHIFT 19
#define TSIZ_NTD_MASK (0xff << 8)
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