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[src/trunk]: src/sys/arch/aarch64 Add a speculation barrier after the 'eret'.
details: https://anonhg.NetBSD.org/src/rev/9d608269cd66
branches: trunk
changeset: 847373:9d608269cd66
user: ryo <ryo%NetBSD.org@localhost>
date: Fri Dec 20 07:16:43 2019 +0000
description:
Add a speculation barrier after the 'eret'.
Some aarch64 cpus speculatively execute instructions after 'eret',
and this potentiates side-channel attack.
from
https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8
diffstat:
sys/arch/aarch64/aarch64/cpuswitch.S | 8 ++++----
sys/arch/aarch64/include/asm.h | 11 ++++++++++-
2 files changed, 14 insertions(+), 5 deletions(-)
diffs (61 lines):
diff -r f6af0daed86d -r 9d608269cd66 sys/arch/aarch64/aarch64/cpuswitch.S
--- a/sys/arch/aarch64/aarch64/cpuswitch.S Fri Dec 20 04:04:25 2019 +0000
+++ b/sys/arch/aarch64/aarch64/cpuswitch.S Fri Dec 20 07:16:43 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.12 2019/09/15 07:13:37 skrll Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.13 2019/12/20 07:16:43 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -37,7 +37,7 @@
#include "opt_ddb.h"
#include "opt_kasan.h"
-RCSID("$NetBSD: cpuswitch.S,v 1.12 2019/09/15 07:13:37 skrll Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.13 2019/12/20 07:16:43 ryo Exp $")
/*
* At IPL_SCHED:
@@ -268,7 +268,7 @@
ldp x1, x2, [x0, #TF_X1]
ldr x0, [x0, #TF_X0]
- eret
+ ERET
END(el1_trap_exit)
#ifdef DDB
END(el1_trap)
@@ -339,7 +339,7 @@
unwind_x0_x2
/* leave sp at l_md.md_utf, return back to EL0 user process */
- eret
+ ERET
END(el0_trap_exit)
#ifdef DDB
END(el0_trap)
diff -r f6af0daed86d -r 9d608269cd66 sys/arch/aarch64/include/asm.h
--- a/sys/arch/aarch64/include/asm.h Fri Dec 20 04:04:25 2019 +0000
+++ b/sys/arch/aarch64/include/asm.h Fri Dec 20 07:16:43 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: asm.h,v 1.4 2019/08/05 16:24:48 joerg Exp $ */
+/* $NetBSD: asm.h,v 1.5 2019/12/20 07:16:43 ryo Exp $ */
#ifndef _AARCH64_ASM_H_
#define _AARCH64_ASM_H_
@@ -8,6 +8,15 @@
#ifdef __aarch64__
#define fp x29
#define lr x30
+
+/*
+ * Add a speculation barrier after the 'eret'.
+ * Some aarch64 cpus speculatively execute instructions after 'eret',
+ * and this potentiates side-channel attacks.
+ */
+#define ERET \
+ eret; dsb sy; isb
+
#endif
#endif /* !_AARCH64_ASM_H_ */
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