[src/trunk]: src/sys/arch/arm/arm Dont use magic number.

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/d32ebc0de873
branches:  trunk
changeset: 808913:d32ebc0de873
user:      skrll <skrll%NetBSD.org@localhost>
date:      Sun Jun 07 12:01:41 2015 +0000

description:
Dont use magic number.

No functional change.

diffstat:

 sys/arch/arm/arm/cpufunc_asm_armv7.S |  27 +++++++++++++++++++++++----
 1 files changed, 23 insertions(+), 4 deletions(-)

diffs (48 lines):

diff -r 8d717d327054 -r d32ebc0de873 sys/arch/arm/arm/cpufunc_asm_armv7.S
--- a/sys/arch/arm/arm/cpufunc_asm_armv7.S      Sun Jun 07 11:46:56 2015 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_armv7.S      Sun Jun 07 12:01:41 2015 +0000
@@ -45,12 +45,31 @@
        bx      lr
 END(armv7_wait)
 
+
+#define        TTBR_C                  (1 << 0)
+#define        TTBR_S                  (1 << 1)
+#define        TTBR_IMP                (1 << 2)
+#define        TTBR_RGN_MASK           (3 << 3)
+#define         TTBR_RGN_NC            (0 << 3)
+#define         TTBR_RGN_WBWA          (1 << 3)
+#define         TTBR_RGN_WT            (2 << 3)
+#define         TTBR_RGN_WBNWA         (3 << 3)
+#define        TTBR_NOS                (1 << 5)
+#define        TTBR_IRGN_MASK          ((1 << 6) | (1 << 0))
+#define         TTBR_IRGN_NC           ((0 << 6) | (0 << 0))
+#define         TTBR_IRGN_WBWA         ((0 << 6) | (1 << 0))
+#define         TTBR_IRGN_WT           ((1 << 6) | (0 << 0))
+#define         TTBR_IRGN_WBNWA        ((1 << 6) | (1 << 0))
+
+#define        TTBR_UPATTR             (TTBR_S | TTBR_RGN_WBNWA | TTBR_C)
+#define        TTBR_MPATTR             (TTBR_S | TTBR_RGN_WBNWA /* | TTBR_NOS */ | TTBR_IRGN_WBNWA)
+
 ENTRY(armv7_context_switch)
        dsb                             @ data synchronization barrier
        mrc     p15, 0, ip, c0, c0, 5   @ get MPIDR
        cmp     ip, #0
-       orrlt   r0, r0, #0x5b           @ MP, cachable (Normal WB)
-       orrge   r0, r0, #0x1b           @ Non-MP, cacheable, normal WB
+       orrlt   r0, r0, #TTBR_MPATTR    @ MP, cachable (Normal WB)
+       orrge   r0, r0, #TTBR_UPATTR    @ Non-MP, cacheable, normal WB
        mcr     p15, 0, r0, c2, c0, 0   @ set the new TTBR 0
 #ifdef ARM_MMU_EXTENDED
        cmp     r1, #0
@@ -126,8 +145,8 @@
 ENTRY_NP(armv7_setttb)
        mrc     p15, 0, ip, c0, c0, 5   @ get MPIDR
        cmp     ip, #0
-       orrlt   r0, r0, #0x5b           @ MP, cachable (Normal WB)
-       orrge   r0, r0, #0x1b           @ Non-MP, cacheable, normal WB
+       orrlt   r0, r0, #TTBR_MPATTR    @ MP, cachable (Normal WB)
+       orrge   r0, r0, #TTBR_UPATTR    @ Non-MP, cacheable, normal WB
        mcr     p15, 0, r0, c2, c0, 0   @ load new TTBR 0
 #ifdef ARM_MMU_EXTENDED
        cmp     r1, #0