[src/trunk]: src/sys/arch/arm/arm32 Rely on the cache operations to perform t...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/429ceac287b5
branches:  trunk
changeset: 830277:429ceac287b5
user:      skrll <skrll%NetBSD.org@localhost>
date:      Sat Mar 03 18:11:25 2018 +0000

description:
Rely on the cache operations to perform the necessary barriers.

diffstat:

 sys/arch/arm/arm32/bus_dma.c |  6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)

diffs (32 lines):

diff -r d9dcb024c844 -r 429ceac287b5 sys/arch/arm/arm32/bus_dma.c
--- a/sys/arch/arm/arm32/bus_dma.c      Sat Mar 03 16:16:24 2018 +0000
+++ b/sys/arch/arm/arm32/bus_dma.c      Sat Mar 03 18:11:25 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: bus_dma.c,v 1.103 2018/03/03 16:16:24 skrll Exp $      */
+/*     $NetBSD: bus_dma.c,v 1.104 2018/03/03 18:11:25 skrll Exp $      */
 
 /*-
  * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
 #include "opt_arm_bus_space.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.103 2018/03/03 16:16:24 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.104 2018/03/03 18:11:25 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -867,13 +867,11 @@
         */
        case BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE:
                STAT_INCR(sync_postreadwrite);
-               arm_dmb();
                cpu_dcache_inv_range(va, len);
                cpu_sdcache_inv_range(va, pa, len);
                break;
        case BUS_DMASYNC_POSTREAD:
                STAT_INCR(sync_postread);
-               arm_dmb();
                cpu_dcache_inv_range(va, len);
                cpu_sdcache_inv_range(va, pa, len);
                break;